A signal generator includes a first amplifier for outputting an amplified voltage in response to a reference voltage and a feedback voltage, a divider circuit for dividing the amplified voltage to generate a divided voltage and the feedback voltage, and a buffer group for outputting a common sensing signal in response to the amplified voltage and outputting a sensing signal in response to the divided voltage, and a memory device including the signal generator.

A signal generator includes a first amplifier for outputting an amplified voltage in response to a reference voltage and a feedback voltage, a divider circuit for dividing the amplified voltage to generate a divided voltage and the feedback voltage, and a buffer group for outputting a common sensing signal in response to the amplified voltage and outputting a sensing signal in response to the divided voltage, and a memory device including the signal generator.

A memory system includes a memory device and a memory controller. The memory device includes a memory cell array configured to store data, a data input and output interface configured to receive a command, an address, and data to be written into the memory cell array from the memory controller, and to output data read from the memory cell array to the memory controller, and a control circuit configured to control the memory cell array to perform an operation in response to receipt of a command while a first control signal is being asserted by the memory controller and receipt of an address subsequent to the command while a second control signal is being asserted by the memory controller.

A memory system includes a memory device and a memory controller. The memory device includes a memory cell array configured to store data, a data input and output interface configured to receive a command, an address, and data to be written into the memory cell array from the memory controller, and to output data read from the memory cell array to the memory controller, and a control circuit configured to control the memory cell array to perform an operation in response to receipt of a command while a first control signal is being asserted by the memory controller and receipt of an address subsequent to the command while a second control signal is being asserted by the memory controller.

Connection weight coefficients to be used in a neural network computation are stored in a memory array. A word line drive circuit drives a word line corresponding to input data of a neural network. A column selection circuit connects to a computation circuit bit lines to which a connection weight coefficient to be computed is connected. The computation circuit determines the sum of cell currents flowing in the bit lines. A result of the determination made by the computation circuit is stored in an output holding circuit, and is set as an input of a neural network in the next layer, to the word line drive circuit. A control circuit instructs the word line drive circuit and the column selection circuit to select the word line and the bit line to be used in the neural network computation, based on information held in a network configuration information holding circuit.

A semiconductor memory device and a memory system are provided. The semiconductor memory device includes a fingerprint read signal generator configured to generate a fingerprint read signal in response to a refresh counting control signal, a memory cell array comprising a plurality of sub memory cell array blocks, a fingerprint output unit configured to receive data output from memory cells connected to one selected among a plurality of word lines and one selected among a plurality of bit lines of one among the plurality of sub memory cell array blocks in response to the fingerprint read signal to generate fingerprint data, and a pseudorandom number generator configured to perform a linear feedback shifting operation in response to an active command to generate sequence data, receive the fingerprint data in response to the fingerprint read signal, and generate the sequence data based on the fingerprint data.

A memory device according to an embodiment includes a fluid layer extending in a first direction, a particle in the fluid layer, a first control electrode made of a first material, a first insulating film provided between the fluid layer and the first control electrode, a second control electrode made of a second material and provided to be spaced apart from the first control electrode in the first direction, a second insulating film provided between the fluid layer and the second control electrode, a third control electrode made of a third material different from the first material and the second material and provided between the first control electrode and the second control electrode, and a third insulating film provided between the fluid layer and the third control electrode.

A nonvolatile memory device includes a memory cell array and a row decoder. The memory cell array includes a plurality of mats. A first cell string of first mat is connected to a plurality of first word-lines, a first bit-line and a first string selection line. A second cell string of second mat is connected to a plurality of second word-lines, a second bit-line and a second string selection line. Each of the first and second cell strings includes a ground selection transistor, memory cells, and a string selection transistor coupled in series. The row decoder applies a first voltage to a third word-line among the plurality of first and second word-lines for a first period of time in a single mat mode and to apply a second voltage to the third word-line for a second period of time longer than the first period of time in a multi-mat mode.

A nonvolatile memory device includes a memory cell array and a row decoder. The memory cell array includes a plurality of mats. A first cell string of first mat is connected to a plurality of first word-lines, a first bit-line and a first string selection line. A second cell string of second mat is connected to a plurality of second word-lines, a second bit-line and a second string selection line. Each of the first and second cell strings includes a ground selection transistor, memory cells, and a string selection transistor coupled in series. The row decoder applies a first voltage to a third word-line among the plurality of first and second word-lines for a first period of time in a single mat mode and to apply a second voltage to the third word-line for a second period of time longer than the first period of time in a multi-mat mode.

Methods, systems, and devices for full multi-plane operation enablement are described. A flash controller can determine that a first plane of a set of planes of a memory die is an invalid plane. The flash controller can issue a single descriptor associated with a multi-plane operation for the set of planes of the memory die. The single descriptor can include a plurality of commands for the multi-plane operation in which the first command of the plurality of commands can be a duplicate of a second command of the plurality of commands based on the first plane being the invalid plane. In some cases, a negative-and (NAND) controller can receive the single descriptor associated with the multi-plane operation for the set of planes of a memory die. The NAND controller can issue a plurality of commands for the multi-plane operation based on receiving the single descriptor.