The disclosure provides an anti-fuse device including an anti-fuse unit and a sensing circuit. The anti-fuse unit includes a first anti-fuse and a second anti-fuse serially connected between a first terminal of the anti-fuse unit and a second terminal of the anti-fuse unit. The sensing circuit is coupled to the first terminal and the second terminal of the anti-fuse unit for sensing a blown state of the anti-fuse unit.

Various embodiments of the present disclosure relate to a non-volatile memory device including a sense amplifier and an operation method thereof. The non-volatile memory device may include: a memory cell array comprising a plurality of memory cells; and the sense amplifier configured to read data of the plurality of memory cells and output the read data. The sense amplifier may include: a first stage sense amplifier configured to sense a voltage difference between a reference voltage and a voltage of a bit line connected to at least one memory cell among the plurality of memory cells, and perform a primary amplification of the sensed voltage difference; and a second stage sense amplifier configured to perform a secondary amplification of a first result of the primary amplification and output a second result of the secondary amplification.

Various embodiments of the present disclosure relate to a non-volatile memory device including a sense amplifier and an operation method thereof. The non-volatile memory device may include: a memory cell array comprising a plurality of memory cells; and the sense amplifier configured to read data of the plurality of memory cells and output the read data. The sense amplifier may include: a first stage sense amplifier configured to sense a voltage difference between a reference voltage and a voltage of a bit line connected to at least one memory cell among the plurality of memory cells, and perform a primary amplification of the sensed voltage difference; and a second stage sense amplifier configured to perform a secondary amplification of a first result of the primary amplification and output a second result of the secondary amplification.

Embodiments described herein include a sensor control device configured for secure over-the-air (OTA) programming. Embodiments include a sensor control device that includes one or more processors, an analyte sensor, a communication module, and a memory. The memory includes a first set of storage blocks that are in a non-programmable state and a second set of blocks that are in a programmable state. The processors are configured to receive, using the communication module, instructions to write marking data to the memory to mark a first storage block from the first set of storage blocks as inaccessible and to write program data to a second storage block from the second set of storage blocks, causing the second storage block to be placed into the non-programmable state. The program data written to the second storage block includes instructions that cause the processors to process analyte data received from the analyte sensor.

Fuses can store different delay states to cause execution of a command to be staggered for different memory dies of a memory package. Fuse arrays can be included in the memory package and programmed to cause execution of a command to be delayed by different amounts for different dies. The fuse arrays can be fabricated and then programmed to cause different delays for different dies.

Fuses can store different delay states to cause execution of a command to be staggered for different memory dies of a memory package. Fuse arrays can be included in the memory package and programmed to cause execution of a command to be delayed by different amounts for different dies. The fuse arrays can be fabricated and then programmed to cause different delays for different dies.

In an anti-fuse memory reading circuit with controllable reading time, a reading time control circuit generates a control signal corresponding to reading time. Based on a clock signal, a programmable reading pulse generation circuit generates a reading pulse with a pulse width corresponding to the control signal. Based on the reading pulse and the control signal, the reading amplification circuit selects a pull-up current source corresponding to the reading time, pulls up a voltage on a bit line (BL) of an anti-fuse memory cell, reads data stored in the anti-fuse memory cell starting from a rising edge of the reading pulse, and latches the read data at a falling edge of the reading pulse. The anti-fuse memory reading circuit can generate a reading pulse with a corresponding pulse width and a pull-up current source with a corresponding size based on the required reading time.

Embodiment provides an anti-fuse memory. An inverting input terminal of an operational amplifier is connected to a feedback terminal of a bias voltage generation module. A voltage across a second input terminal may be obtained according to a voltage across the feedback terminal. The second input terminal is electrically connected to an output terminal of the operational amplifier. The voltage across the second input terminal serves as a bias voltage across a read module. A circuit between a second power supply terminal and the feedback terminal is equivalent to a circuit between a monitoring terminal and a first power supply terminal, and a circuit between the feedback terminal and an adjustable resistor is equivalent to a circuit between the monitoring terminal and an anti-fuse memory cell.

Embodiment provides an anti-fuse memory. An inverting input terminal of an operational amplifier is connected to a feedback terminal of a bias voltage generation module. A voltage across a second input terminal may be obtained according to a voltage across the feedback terminal. The second input terminal is electrically connected to an output terminal of the operational amplifier. The voltage across the second input terminal serves as a bias voltage across a read module. A circuit between a second power supply terminal and the feedback terminal is equivalent to a circuit between a monitoring terminal and a first power supply terminal, and a circuit between the feedback terminal and an adjustable resistor is equivalent to a circuit between the monitoring terminal and an anti-fuse memory cell.

In an example, a multiplexer is provided. The multiplexer may include one or more first strings controlling access to source-lines of the memory, wherein a first string of the one or more first strings includes a first set of two high voltage transistors and a first plurality of low voltage transistors. The multiplexer may include one or more second strings controlling access to bit-lines of the memory, wherein a second string of the one or more second strings includes a second set of two high voltage transistors and a second plurality of low voltage transistors. A method for operating such multiplexer is provided.