Embodiment provides an anti-fuse memory. An inverting input terminal of an operational amplifier is connected to a feedback terminal of a bias voltage generation module. A voltage across a second input terminal may be obtained according to a voltage across the feedback terminal. The second input terminal is electrically connected to an output terminal of the operational amplifier. The voltage across the second input terminal serves as a bias voltage across a read module. A circuit between a second power supply terminal and the feedback terminal is equivalent to a circuit between a monitoring terminal and a first power supply terminal, and a circuit between the feedback terminal and an adjustable resistor is equivalent to a circuit between the monitoring terminal and an anti-fuse memory cell.

Embodiment provides an anti-fuse memory. An inverting input terminal of an operational amplifier is connected to a feedback terminal of a bias voltage generation module. A voltage across a second input terminal may be obtained according to a voltage across the feedback terminal. The second input terminal is electrically connected to an output terminal of the operational amplifier. The voltage across the second input terminal serves as a bias voltage across a read module. A circuit between a second power supply terminal and the feedback terminal is equivalent to a circuit between a monitoring terminal and a first power supply terminal, and a circuit between the feedback terminal and an adjustable resistor is equivalent to a circuit between the monitoring terminal and an anti-fuse memory cell.

In an example, a multiplexer is provided. The multiplexer may include one or more first strings controlling access to source-lines of the memory, wherein a first string of the one or more first strings includes a first set of two high voltage transistors and a first plurality of low voltage transistors. The multiplexer may include one or more second strings controlling access to bit-lines of the memory, wherein a second string of the one or more second strings includes a second set of two high voltage transistors and a second plurality of low voltage transistors. A method for operating such multiplexer is provided.

A memory device includes a first transistor. The first transistor includes one or more first semiconductor nanostructures spaced apart from one another along a first direction. Each of the one or more first semiconductor nanostructures has a first width along a second direction perpendicular to the first direction. The memory device also includes a second transistor coupled to the first transistor in series. The second transistor includes one or more second semiconductor nanostructures spaced apart from one another along the first direction. Each of the one or more second semiconductor nanostructures has a second, different width along the second direction.

A memory device includes a first transistor. The first transistor includes one or more first semiconductor nanostructures spaced apart from one another along a first direction. Each of the one or more first semiconductor nanostructures has a first width along a second direction perpendicular to the first direction. The memory device also includes a second transistor coupled to the first transistor in series. The second transistor includes one or more second semiconductor nanostructures spaced apart from one another along the first direction. Each of the one or more second semiconductor nanostructures has a second, different width along the second direction.

Memory devices, systems including memory devices, and methods of operating memory devices are described, in which security measures may be implemented to control access to a fuse array (or other secure features) of the memory devices based on a secure access key. In some cases, a customer may define and store a user-defined access key in the fuse array. In other cases, a manufacturer of the memory device may define a manufacturer-defined access key (e.g., an access key based on fuse identification (FID), a secret access key), where a host device coupled with the memory device may obtain the manufacturer-defined access key according to certain protocols. The memory device may compare an access key included in a command directed to the memory device with either the user-defined access key or the manufacturer-defined access key to determine whether to permit or prohibit execution of the command based on the comparison.

A semiconductor memory device includes a memory cell array, a memory apparatus and a power-on operation apparatus, and is capable of knowing whether a reading of the setting information which is set during the power-on operation had been completed correctly or not. The flash memory reads the fuse memory when it is detected that the power supply has reached the power-on detection level, and determines whether the reading of the fuse memory had been completed correctly. When not completed correctly, the fuse memory is read again within the maximum read count, and the setting information (which was read from the fuse memory) is written into the CF register. The identification information (that identifies whether the reading of the fuse memory has been completed correctly or not) is stored in the register.

A memory device and a method of correcting error in a memory device is provided. The memory device controller includes a memory array, a tie-breaker array, a write controller, a verify circuit, and a controller. The memory array includes a plurality of memory cells. The tie-breaker array includes a plurality of tie-breaker rows. The write controller is configured to apply a programming voltage to the memory array. The verify circuit is configured to apply a verify voltage to verify whether the memory cells in the memory array are in an unambiguous state or not. The controller is configured to enable one or more tie-breaker rows in additions to the memory array to adjust an output of the memory array when the memory cells in the memory array are in an ambiguous state.

A one-time programmable memory cell includes a transistor coupled to a capacitor. The transistor includes at least one first conductive gate element arranged in at least one first trench formed in a semiconductor substrate, and at least one first channel portion buried in the substrate and extending at the level of at least a first lateral surface of the at least one first conductive gate element. The capacitor includes a capacitive element forming a memory. The at least one first channel portion is electrically coupled to an electrode of the capacitive element.

A latch circuit includes a latch module, a set control module, a reset control module and a clock module, wherein the latch module is employed for latching data input by a data module, the set control module is employed for controlling the latch module to output a high-level signal, the reset control module is employed for controlling the latch module to output a low-level signal, and the clock module is employed for providing a readout clock signal to the latch module.