Patent classifications
G11C19/08
FERRIMAGNETIC HEUSLER COMPOUNDS WITH HIGH SPIN POLARIZATION
A magnetic device and method for providing the magnetic device are disclosed. The magnetic device includes a multilayer structure and a magnetic layer. The multilayer structure includes alternating layers of A and E. A includes a first material. The first material includes at least one of Co, Ru, or Ir. The first material may include an IrCo alloy. E includes at least one other material that includes Al. The other material(s) may include an alloy selected from AlGa, AlSn, AlGe, AlGaGe, AlGaSn, AlGeSn, and AlGaGeSn. A composition of the multilayer structure is represented by A.sub.1-xE.sub.x, where x is at least 0.45 and not more than 0.55. The magnetic layer includes an Al-doped Heusler compound. The magnetic layer shares an interface with the multilayer structure.
SWITCHING DEVICE AND RESISTANCE VARIABLE DEVICE
A switching device according to an embodiment includes a switching layer disposed between a first electrode and a second electrode. The switching layer contains a material containing a first cation element Z, Te, and N. This material contains at least 5 atomic % or more of each of Z, Te, and N, and when an atomic ratio of Te is X, an atomic ratio of N is Y, an atomic ratio of Z is W, a ratio of Z.sub.2Te.sub.3 to ZN on a straight line connecting a compound of the first cation element Z with tellurium and nitride of the first cation element Z in a ternary phase diagram of Z, Te, and N is A, and a change in an N content from the Z.sub.2Te.sub.3-ZN line is B, the material has a composition satisfying X=1.2 (1−A) (0.5+B), Y=A (0.5+B), and W=1−X−Y, where −0.06≤B≤0.06 is satisfied when ⅓>A and ¾<A, and −0.06≤B and Y≤0.45 are satisfied when ⅓≤A≤¾.
Content addressable memory with spin-orbit torque devices
Ternary content addressable memory (TCAM) circuits are provided herein. In one example implementation, a TCAM circuit can include a first spin-orbit torque (SOT) magnetic tunnel junction (MTJ) element having a pinned layer coupled to a first read transistor controlled by a first search line, and having a spin hall effect (SHE) layer coupled in a first configuration across complemented write inputs. The TCAM circuit can include a second SOT MTJ element having a pinned layer coupled to a second read transistor controlled by a second search line, and having a SHE layer coupled in a second configuration across the complemented write inputs. The TCAM circuit can include a bias transistor configured to provide a bias voltage to drain terminals of the first read transistor and the second read transistor, and a voltage keeper element that couples the drain terminals to a match indicator line.
SEMICONDUCTOR DEVICE WITH FIRST-IN-FIRST-OUT CIRCUIT
Apparatuses including a first-in first-out circuit are described. An example apparatus includes: a first-in first-out circuit including a first latch, a second latch and a logic circuit coupled in series. The first latch receives first data and latches the first data responsive to a first input pointer signal. The second latch receives the latched first data from the first latch and latches the received first data responsive to a second input pointer signal that has a different phase from the first input pointer signal and thus provides a second data. The logic circuit receives the second data and an output pointer signal and further provides an output data responsive to the output pointer signal.
Magnetic storage device
A magnetic storage device includes a magnetic body including first and second magnetic regions and a magnetic connection region that connects the first and second magnetic regions, and in which a plurality of magnetic domains each storing information by a magnetization direction thereof is formed, a read element that is electrically connected to the magnetic connection region and by which a magnetization direction of one of the magnetic domains is read, and a write element by which a magnetic domain having a magnetization direction is formed in the magnetic body according to information to be stored. The magnetic domains formed in each of the first and second magnetic regions are shifted in a predetermined direction in response to current that flows through the corresponding one of the first and second magnetic regions.
MEMORY SYSTEM AND SHIFT REGISTER MEMORY
According to one embodiment, a memory system includes a shift register memory and a controller. The shift register memory includes data storing shift strings. The controller changes a shift pulse, which is to be applied to the data storing shift strings from which first data is read by applying a first shift pulse, to a second shift pulse to write second data to the data storing shift strings and to read the second data from the data storing shift strings. The controller creates likelihood information of data read from the data storing shift strings in accordance with a read result of the second data. The controller performs soft decision decoding for the first data using the likelihood information.
Memory system for controlling magnetic memory
According to one embodiment, a magnetic memory puts a first magnetic domain having a magnetization direction which is the same as or opposite to a magnetic domain of a first layer of a magnetic memory line, into the first layer, based on a value of data and the magnetization direction of the first layer. When receiving a first command, the magnetic memory puts a first additional magnetic domain and a second additional magnetic domain having a magnetization direction opposite to the first additional magnetic domain into the magnetic memory line. When receiving a second command, the magnetic memory read the first and second additional magnetic domains to determine the magnetization direction of the first magnetic domain.
Memory Devices Comprising Magnetic Tracks Individually Comprising A Plurality Of Magnetic Domains Having Domain Walls And Methods Of Forming A Memory Device Comprising Magnetic Tracks Individually Comprising A Plurality Of Magnetic Domains Having Domain Walls
A method of forming a memory device having magnetic tracks individually comprising a plurality of magnetic domains having domain walls, includes forming an elevationally outer substrate material of uniform chemical composition. The uniform composition material is partially etched into to form alternating regions of elevational depressions and elevational protrusions in the uniform composition material. A plurality of magnetic tracks is formed over and which angle relative to the alternating regions. Interfaces of immediately adjacent of the regions individually form a domain wall pinning site in individual of the magnetic tracks. Other methods, including memory devices independent of method, are disclosed.
Spin transfer torque switching of a magnetic layer with volume uniaxial magnetic crystalline anistotropy
A device is disclosed. The device includes a first magnetic layer and a tunnel barrier. The first magnetic layer has a volume uniaxial magnetic crystalline anisotropy. The magnetic moment of the first layer is substantially perpendicular to the first layer. The tunnel barrier is in proximity to the first magnetic layer. The orientation of the magnetic moment of the first magnetic layer is reversed by spin transfer torque induced by current passing between and through the first magnetic layer and the tunnel barrier.
Linear input and non-linear output majority logic gate with and/or function
A new class of logic gates are presented that use non-linear polar material. The logic gates include multi-input majority gates and threshold gates. Input signals in the form of analog, digital, or combination of them are driven to first terminals of non-ferroelectric capacitors. The second terminals of the non-ferroelectric capacitors are coupled to form a majority node. Majority function of the input signals occurs on this node. The majority node is then coupled to a first terminal of a capacitor comprising non-linear polar material. The second terminal of the capacitor provides the output of the logic gate, which can be driven by any suitable logic gate such as a buffer, inverter, NAND gate, NOR gate, etc. Any suitable logic or analog circuit can drive the output and inputs of the majority logic gate. As such, the majority gate of various embodiments can be combined with existing transistor technologies.