The present disclosure provides a scan driving circuit for driving an Nth-stage scanning line including: a pull-up control module for receiving a cascade signal of an upper stage and generating a scan level signal of the Nth-stage scanning line based on the cascade signal of the upper stage; a pull-up module for pulling down the scanning signal of the Nth-stage scanning line when the first clock signal is low according to the scan level signal and the first clock signal; the pull-up control module includes a first control unit and a second control unit, the control terminal of the second control unit inputs a second clock signal for controlling the scan level signal to become smaller when the second clock signal is at a high level. The present disclosure can prevent the waveform of the gate from appearing spikes, and thus the waveform of the gate is output normally.

A shift register unit, a shift register, a gate driving circuit and a display device are discloses. The shift register unit has an output node Out(n) of a current stage, a pull-up node PU and a pull-down node PD, and the shift register unit includes a first capacitor module C1, a pull-down module and a pull-down control module, and the pull-down control module is configured to output one of a high level signal and a low level signal to the pull-down node (PD) in accordance with a current operating phase.

Provided are an array substrate, a display panel and a display device, and the array substrate includes: at least one pressure sensor disposed in the non-display region; and the pressure sensor includes a first resistor, a second resistor, a third resistor and a fourth resistor; and a plurality of shift registers disposed in the non-display region, and the first resistor, the second resistor, the third resistor and the fourth resistor are disposed at least one of following positions: inside the shift register, between adjacent two of the plurality of shift registers, at a side of the plurality of shift registers close to the display region, and at a side of the plurality of shift registers away from the display region.

A display device may include a plurality of rows of pixels configured to display image data on a display and a first gate driver circuit. The first gate driver circuit may couple a first voltage source to a first node associated with a first gate of a first switch upon receipt of a start signal or a gate signal from another gate driver circuit and couple a first clock signal to a first gate line via the first switch after a first voltage of the first node exceeds a threshold. The threshold is associated with activating the first switch, such that the first gate line is configured to couple to a first row of the plurality of rows of pixels. The first gate driver circuit may then couple a second voltage source to the first node based on a second clock signal, such that the second voltage source discharges the first node.

A scan driving circuit, including a multi-stage shift register unit that outputs scan signals by stage under control of a clock signal (CKR, CKBR), the shift register unit includes an output terminal for outputting the scan signals, the scan driving circuit further includes a multi-stage signal generating unit, with an n-th stage signal generating unit is connected respectively to an output terminal of an n-th stage shift register unit and an output terminal of an (n+j)-th stage shift register unit, the n-th stage signal generating unit is configured to convert an outputted first level into a second level under triggering of a scan signal outputted by the n-th stage shift register unit, and convert an outputted second level into a first level under triggering of a scan signal outputted by the (n+j)-th stage shift register unit; the n and j both are positive integers.