A display panel and a display drive method thereof, and a display device are provided. The display panel includes a plurality of display regions and a plurality of scan drive circuits, the plurality of display regions includes a first display region and a second display region that are parallel to each other and do not overlap with each other, and the plurality of scan drive circuits includes a first scan drive circuit and a second scan drive circuit, the first and second display regions are connected to the first and second scan drive circuits to respectively receive a first light-emitting control signal, and the display drive method includes: individually adjusting a pulse width of at least one of the first light-emitting control signal and the second light-emitting control signal to adjust the light-emitting durations of light-emitting elements of the first and second display regions within one display period, respectively.

In a method of using an ultrasonic sensor comprising a two-dimensional array of ultrasonic transducers, a plurality of ultrasonic signals are transmitted according to a beamforming pattern at a position of the two-dimensional array. The beamforming pattern focuses the plurality of ultrasonic signals to location above the two-dimensional array, wherein the beamforming pattern identifies ultrasonic transducers of the two-dimensional array that are activated during transmission of the ultrasonic signals, and wherein at least some ultrasonic transducers of the beamforming pattern are phase delayed with respect to other ultrasonic transducers of the beamforming pattern. At least one reflected ultrasonic signal is received at the position according to a receive pattern, wherein the receive pattern identifies at least one ultrasonic transducers of the two-dimensional array that is activated during the receiving. The transmitting and the receiving are repeated at a plurality of positions of the two-dimensional array.

A transistor whose channel region includes an oxide semiconductor is used as a pull down transistor. The band gap of the oxide semiconductor is 2.0 eV or more, preferably 2.5 eV or more, more preferably 3.0 eV or more. Thus, hot carrier degradation in the transistor can be suppressed. Accordingly, the circuit size of the semiconductor device including the pull down transistor can be made small. Further, a gate of a pull up transistor is made to be in a floating state by switching of on/off of the transistor whose channel region includes an oxide semiconductor. Note that when the oxide semiconductor is highly purified, the off-state current of the transistor can be 1 aA/μm (1×10.sup.−18 A/μm) or less. Therefore, the drive capability of the semiconductor device can be improved.

The present disclosure provides a shift register, the register including n stages, each being configured for performing forward and reverse operations, wherein in the forward operation, a gate signal is output in a forward direction, wherein in the reverse operation, a gate signal is output in a reverse direction, wherein a n-th stage among the n stages includes: a charging unit configured for charging a Q node in a response to a reception of a forward start signal or a reverse start signal; a gate signal output unit configured for outputting a gate signal in a response to the Q node being charged by the charging unit; and a discharging unit configured for discharging the Q node after the output unit has outputted the gate signal, wherein the charging unit includes a dummy transistor and a reverse start transistor, both being connected to the Q node.

Provided is a display panel. The display panel includes multiple scanning lines, a gate driver circuit, and a timing controller. The timing controller is configured to: receive multiple data enable signals, generate a gate control signal, and provide the gate control signal for the gate driver circuit. The gate control signal includes a start signal, a first clock signal and a second clock signal. The multiple data enable signals are only within the active cycle. The timing controller is configured to generate a rising edge of the start signal within the vertical blanking cycle of the (N−1).sup.th frame cycle. Alternatively, the timing controller is configured to generate a rising edge and a falling edge of the start signal within a time interval formed by a rising edge and a falling edge of a first data enable signal in the N.sup.th frame cycle.

A display panel and a display device are provided. The display panel includes a driving circuit. The driving circuit includes N-level shift registers cascaded with each other, where N is greater than or equal to two. A shift register includes: a first control unit configured to receive an input signal and control a signal of a first node; a second control unit configured to receive a first voltage signal and control a signal of a second node; a third control unit configured to receive the first voltage signal and generate an output signal, or receive a second voltage signal and generate an output signal in response to a signal of a third node connected to the first node; and a fourth control unit configured to receive the second voltage signal and control the signal of the first node. The first and second voltage signals are high-level and low-level signals, respectively.

A display substrate, a display panel and a display device. A pixel circuit includes a power supply wire providing a power supply voltage to the display pixel; a drive circuit in the non-display region includes a drive signal wire providing a drive signal to the pixel circuit; the power supply wire includes a narrow wire portion overlapping with the drive signal wire and a wide wire portion; a wire width of the narrow wire portion is less than that of the wide wire portion; the display substrate has a first side for display and a second side opposite to the first side, includes a bending region at an edge of the base substrate; the power supply wire and the drive signal wire extend from the first side to the bending region, crossing the bending region to extend to the second side; the narrow wire portion is on the second side.

Provided are a display panel and a display device. The display panel includes a first display region, a second display region and a non-display region between the first display region and the second display region. The display panel further includes a third display region. The third display region and the non-display region at least partially overlap in the light emission direction of the display panel. In the preceding solution, the third display region is added in the display panel, and the third display region and the non-display region between the first display region and the second display region at least partially overlap in the light emission direction of the display panel, that is, the third display region covers at least part of the joint between the first display region and the second display region.

Embodiments of the present disclosure provide a shift register, a gate driving circuit, and a display apparatus. The shift register comprises a power consumption-reducing sub-circuit and an output sub-circuit; wherein: the power consumption-reducing sub-circuit is connected to a clock signal terminal, a control terminal, and the output sub-circuit, the power consumption-reducing sub-circuit is used to output a signal of the clock signal terminal to the output sub-circuit under the control of the control terminal; the output sub-circuit is connected to the clock signal terminal through the power consumption-reducing sub-circuit and is also connected to an output terminal and a pull-up node, the output sub-circuit is used to output an output signal of the power consumption-reducing sub-circuit to the output terminal under the control of the pull-up node.

A shift register unit, a gate driving circuit, a display device, and a driving method are provided. The shift register unit includes a first input circuit, an output control circuit, and an output circuit. The first input circuit is configured to output a first input signal to a first node in response to a first control signal; the output control circuit is configured to output an output control signal to a second node under control of a level of the first node; and the output circuit includes an output terminal, and the output circuit is configured to output an output signal to the output terminal under control of a level of the second node.