The present disclosure provides a gate drive unit, a driving method thereof and a gate drive circuit. The gate drive unit includes a shift register and a plurality of output control modules. Each of the output control modules is connected to a corresponding clock scanning signal line and a corresponding first scanning signal output terminal, respectively. Each of the output control modules includes a first output control submodule and an output reset submodule. The first output control submodule is connected to a signal output terminal of the shift register, the corresponding clock scanning signal line and the corresponding first scanning signal output terminal, and configured to send a clock scanning signal of the corresponding clock scanning signal line to the corresponding first scanning signal output terminal, under control of a signal outputted by the signal output terminal of the shift register.

A shift register unit, a gate drive circuit, and a drive method are provided. The shift register unit includes a first input circuit, a second input circuit, and an output circuit. The first input circuit is configured to charge a first node in response to a first input signal to control a level of the first node; the second input circuit is configured to charge a second node in response to a second input signal to control a level of the second node; and the output circuit is configured to output an output signal to an output terminal under common control of the level of the first node and the level of the second node.

A gate driving circuit includes a shift unit and a switch unit. The shift unit receives a start input signal, a first clock input signal and a second clock input signal to generate an enable output signal. The switch unit is connected to the shift unit and receiving the enable output signal. The switch unit outputs a third clock signal based on the enable output signal.

An array substrate and a manufacturing method thereof, and a display device are provided. The array substrate includes: a base substrate, and a GOA circuit, a source electrode IC and PLG wires arranged on the base substrate, and the PLG wires connect the GOA circuit with the source electrode IC. The GOA circuit transmits a GOA signal, and the GOA signal comprises a cascade signal and a non-cascade signal. The PLG wires comprise a first PLG wire group and at least one second PLG wire group, the first PLG wire group transmits the cascade signal, the second PLG wire group transmits the non-cascade signal, a line width of the first PLG wire group is smaller than that of the second PLG wire group, and the first PLG wire group is located at a side of the second PLG wire group distal to an active area of the base substrate.

A shift register unit, a scan driving circuit, an array substrate, a display device, and a driving method are provided. The shift register unit includes an input circuit, a replacement circuit, an output circuit, and a pull-down circuit; the input circuit is respectively connected to the input terminal and the first node, and is configured to set the first node to an active level when the input terminal (IN) is at an active level; the replacement circuit is respectively connected to the input terminal and the second node, and is configured to set the second node to an inactive level when the input terminal is at an active level.

A shift register unit and a driving method thereof, a gate drive circuit, and a display device are disclosed. The shift register unit includes a first input sub-circuit, a first control sub-circuit, an output sub-circuit, and a second control sub-circuit. The first input sub-circuit is configured to output a first control signal of the first control signal terminal to the first control sub-circuit; the first control sub-circuit is configured to output a second input signal of the second input terminal to the first node, or the first control sub-circuit is configured to output the second input signal to the second control sub-circuit; the second control sub-circuit is configured to output a second clock signal to the second node; or the second control sub-circuit is configured to output a first voltage of the first voltage terminal to the second node under control of a level of the control node.

A shift register unit and a driving method thereof, a gate driving circuit, and a display device are provided. A shift register unit includes a blanking input circuit, a display input circuit, an output circuit; the blanking input circuit is configured to input a blanking control signal to a first node during a blanking period in response to a blanking input signal, the blanking input circuit includes a charging sub-circuit, the charging sub-circuit is configured to input the blanking control signal to a control node in response to a first compensation control signal and a second compensation control signal, the display input circuit is configured to input a display control signal to the first node during a display period in response to a display input signal; the output circuit is configured to output a composite output signal to an output end under control of a level of the first node.

A shift-register unit circuit (100) includes a first input sub-circuit (120) configured to receive a display-input signal from a display-input terminal (STU2, VDD, VGH) and input a display output-control signal to a first node (Q) based on the display-input signal during a display period of one cycle of displaying one frame of image. The shift-register unit circuit (100) also includes a second input sub-circuit (110) configured to receive a blank-input signal for charging a blank-control node (H), and configured to input a blank-output-control signal to the first node (Q) based on the blank-input signal during a blank period of the one cycle. The shift-register unit circuit (100) further includes an output sub-circuit (130) configured to output a hybrid signal controlled by the first node (Q). The second input sub-circuit (110) is also configured, before an end of the blank period, to receive a first blank-reset signal to reset the blank-control node (H).

A shift register unit and a driving method thereof, a gate drive circuit and a display device. The shift register unit includes a first input circuit, an output circuit and a first output pull-down circuit. The first input circuit is configured to charge a pull-up node in response to a first clock signal and reset the pull-up node in response to the first clock signal; the output circuit is configured to output a second clock signal to an output terminal under a control of a level of the pull-up node; the first output pull-down circuit is configured to denoise the output in response to a third clock signal.

A display apparatus includes: a display panel including a plurality of pixels respectively connected to a plurality of gate lines; a gate driving circuit including a plurality of driving stages configured to apply gate signals to the gate lines; a voltage generator configured to output a gate-on voltage through a voltage output terminal thereof; and a signal controller configured to sense a variation in current of the voltage output terminal to output a back bias control voltage corresponding to the sensed current variation, wherein each of the driving stages comprises a plurality of oxide thin film transistors and at least one of the oxide thin film transistors is a four-terminal transistor in which a threshold voltage thereof is controlled by the back bias control voltage.