A matrix-array detector and to a method for implementing the detector are provided. The detector includes an array of pixels that are sensitive to a physical effect and arranged in a matrix along rows and down columns, each pixel generating a signal according to the physical effect; row conductors, each allowing the pixels of one row to be driven; a first group of driver modules each delivering selection signals to one row conductor of a first group of row conductors; a second group of driver modules each delivering selection signals to one row conductor of a first group of row conductors; the first and second groups of row conductors being interlaced.

A shift register is provided, which includes a blanking input circuit, a blanking control circuit, a blanking pull-down circuit, and a shift register circuit. The blanking input circuit may provide a blanking input signal to a first control node according to a second clock signal. The blanking control circuit may provide a first clock signal to a second control node and maintain a voltage difference between the first control node and the second control node, according to a voltage of the first control node. The blanking pull-down circuit may provide a voltage of the second control node to a pull-down node according to the first clock signal. The shift register circuit may provide a shift signal via a shift signal output terminal and a first drive signal via a first drive signal output terminal according to a voltage of the pull-down node.

The present disclosure provides a gate driving circuit, a method of driving a gate driving circuit, and a display panel. The gate driving circuit includes a plurality of driving units connected in cascade. Each driving unit includes: N shift register units; and a mode control circuit connected to the N shift register units, wherein the mode control circuit is configured to receive a control signal for the driving unit, and connect the N shift register units in one of a plurality of resolution modes under the control of the control signal.

Provided are a display panel and display device. The display panel includes a driver circuit comprising a shift register that is N-stage cascaded; wherein the shift register comprises: a third control unit configured to receive a first voltage signal and generate an output signal in response to a signal of a third node, or receive a second voltage signal and generate an output signal in response to a signal of a second node; and a fourth control comprising a first capacitor and a first transistor, wherein a second plate of the first capacitor is connected to a drain of the first transistor, a first plate of the first capacitor and a gate of the first transistor are connected to a same node; and/or a first plate of the first capacitor and a gate of the first transistor receive a same signal.

Provided are a display panel and display device. The display panel includes a driver circuit comprising a shift register that is N-stage cascaded; wherein the shift register comprises: a third control unit configured to receive a first voltage signal and generate an output signal in response to a signal of a third node, or receive a second voltage signal and generate an output signal in response to a signal of a second node; and a fourth control comprising a first capacitor and a first transistor, wherein a second plate of the first capacitor is connected to a drain of the first transistor, a source of the first transistor receives a first control signal, and a gate of the first transistor receives a second control signal.

Provided are a display panel and a display device. The display panel includes a driving circuit comprising N stages of cascaded shift registers. Each shift register includes a first control unit, a second control unit, a third control unit, and a fourth control unit. The first control unit is configured to receive an input signal and control a signal of a first node. The second control unit is configured to receive a first voltage signal and control a signal of a second node. The third control unit is configured to receive a signal of a fourth node and control an output signal, or receive a second voltage signal and control the output signal. The fourth control unit is configured to receive the first voltage signal and a third voltage signal and control the signal of the fourth node.

A shift-register unit circuit includes a first input sub-circuit configured to have a display-input terminal to receive a display-input signal, and to provide a display output-control signal to a first node; a second input sub-circuit configured to have a blank-input terminal to receive a blank-input signal for charging a blank-control node, and to provide a blank output-control signal to the first node; an output sub-circuit configured to output signal under control of the first node; a first control sub-circuit, configured to control a voltage level of a second node under control of the first node; a second control sub-circuit configured to pull down voltage levels of the first node and the output terminal to turn-off voltage levels under control of the second node; and an anti-leak sub-circuit configured to provide a working voltage level to an anti-leak connection point.

The present disclosure provides a gate drive circuit, an array substrate, and a display device. The gate drive circuit includes cascaded shift registers, control circuits, level shifters, voltage stabilization circuits, and first exchanging circuits. The shift registers at respective stages output respective first signals. Each control circuit is configured to process the respective first signal to generate a respective second signal. Each level shifter is configured to convert the voltage level of the respective second signal to generate a respective third signal. Each voltage stabilization circuit is configured to stabilize the respective third signal. The stabilized third signal is outputted as a fourth signal. The first exchanging circuit is configured to enable any of the following: exchanging the first signals at two adjacent stages, exchanging the second signals at two adjacent stages, exchanging the third signals at two adjacent stages, and exchanging the fourth signals at two adjacent stages.

A display device includes a display panel having a curved side or a polygonal side, the display panel including a plurality of pixels in a display region, a gate driver including a plurality of normal stages connected to each other for outputting gate signals to the pixels via a plurality of gate lines, and a plurality of dummy stages between some of the normal stages, and a data driver providing data signals to the pixels via a plurality of data lines.

A shift register unit and a driving method thereof, a gate driving circuit and a display apparatus are provided. The shift register unit comprises: an input circuit, a transmission circuit and an output control circuit; wherein the transmission circuit is coupled to a first node, a second node, a clock signal terminal and a first power source terminal, respectively, and is configured to control an electric potential of the second node under the control of the first node, the clock signal terminal and the first power source terminal, and the output control circuit is configured to control an electric potential of the output signal terminal under the control of the second node. The electric potential of the output signal from the output signal terminal in the shift register unit can be controlled by adopting one clock signal terminal, which effectively reduces the power consumption of the shift register unit.