The present disclosure provides a gate drive circuit, an array substrate, and a display device. The gate drive circuit includes cascaded shift registers, control circuits, level shifters, voltage stabilization circuits, and first exchanging circuits. The shift registers at respective stages output respective first signals. Each control circuit is configured to process the respective first signal to generate a respective second signal. Each level shifter is configured to convert the voltage level of the respective second signal to generate a respective third signal. Each voltage stabilization circuit is configured to stabilize the respective third signal. The stabilized third signal is outputted as a fourth signal. The first exchanging circuit is configured to enable any of the following: exchanging the first signals at two adjacent stages, exchanging the second signals at two adjacent stages, exchanging the third signals at two adjacent stages, and exchanging the fourth signals at two adjacent stages.

A shift register, a method for driving the same, a gate drive circuitry and a display apparatus are provided. The shift register includes: an input circuit, connected to a signal input terminal, a pull-up node and a first control terminal, and configured to provide a signal of the signal input terminal to the pull-up node under the control of the first control terminal; an output circuit, connected to the pull-up node, a first clock signal terminal and a signal output terminal, and configured to provide a signal of the first clock signal terminal to the signal output terminal under the control of the pull-up node; and a pull-up node control circuit, connected to the pull-up node, a second clock signal terminal, a third clock signal terminal and a first voltage terminal, and configured to provide a signal of the first voltage terminal to the pull-up node.

The present application provides a shift register and a method of driving the same, and a gate driving circuit. The shift register includes a detection sub-shift register. The detection sub-shift register includes: a detection input sub-circuit configured to provide a signal of the first input terminal to the pull-up control node under the control of the first clock signal terminal, and provide a signal of the second clock signal terminal to the first pull-up node under the control of the pull-up control node; and a detection output sub-circuit configured to provide a signal of the third clock signal terminal to the first output terminal under the control of the first pull-up node.

A shift register unit, a gate driving circuit, a display device and a driving method are disclosed. The shift register unit includes an input circuit, a first node reset circuit, an output circuit and a first reset control circuit. The input circuit is configured to provide an input signal to a first node; the first node reset circuit is configured to reset the first node under control of a level of a reset control node; the output circuit is configured to output an output signal at the output terminal under control of a level of the first node; and the first reset control circuit is configured to control the level of the reset control node in response to a reset control signal.

Disclosed are a shift register, a method for fabricating an inverter, a gate driving circuit, and a display device, and the shift register includes a first pull-down circuit, a second pull-down circuit, and a first inverter, where the first pull-down circuit is configured to operate under the control of a first level of a power source terminal, and to be disabled under the control of a second level of the power source terminal; and the first inverter is configured to provide the second pull-down circuit with a signal of a first signal terminal under the control of the first level of the power source terminal to disable the second pull-down circuit, and to provide the second pull-down circuit with a signal of a second signal terminal under the control of the second level of the power source terminal to drive the second pull-down circuit to operate.

A gate driving circuit includes a plurality of stages connected to one another, wherein each of the plurality of stages includes an output unit which outputs a first clock signal as a gate voltage in accordance with a voltage of a Q node and a voltage of a QB node; a first node control unit which controls the voltage of the Q node; and a second node control unit which controls the QB node, wherein the first node control unit includes second and third transistors which discharge the Q node, the second transistor outputs a ground voltage to the Q node in response to a second clock signal, and the third transistor outputs the ground voltage to the Q node in response to the voltage of the QB node.

A gate driving circuit includes a plurality of shift registers coupled in series. An nth shift register includes a driving circuit and a pull-down circuit. The driving circuit is electrically coupled to an output node and a first node. The driving circuit is configured to receive a first clock signal and output a gate signal according to the first clock signal. The pull-down circuit is electrically coupled to the output node. The pull-down circuit is configured to receive an (n−m)th gate signal and an (n+m)th gate signal, and pull-down the gate signal to a low voltage level according to one of the (n−m)th gate signal and the (n+m)th gate signal, wherein m and n are positive integers.

Apparatuses including a first-in first-out circuit are described. An example apparatus includes: a first-in first-out circuit including a first latch, a second latch and a logic circuit coupled in series. The first latch receives first data and latches the first data responsive to a first input pointer signal. The second latch receives the latched first data from the first latch and latches the received first data responsive to a second input pointer signal that has a different phase from the first input pointer signal and thus provides a second data. The logic circuit receives the second data and an output pointer signal and further provides an output data responsive to the output pointer signal.

The present disclosure provides to a shift register unit, a driving method, a gate driving circuit, and a display panel. The shift register unit includes: first and second signal terminals respectively outputting high and low levels alternately, a level logic of a signal output from the second signal terminal being opposite to that from the first signal terminal; first and second pull-down control circuits; a first pull-down circuit coupled to the first pull-down node, the first signal terminal, and a pull-down target node, and transmitting, in response to a signal of the first pull-down node, the signal of the first signal terminal to the pull-down target node; a second pull-down circuit coupled to the second pull-down node, the second signal terminal, and the pull-down target node, and transmitting, in response to a signal of the second pull-down node, the signal of the second signal terminal to the pull-down target node.

The present disclosure provides a display panel and a display device. The display panel includes a gate driving circuit including a first transistor; a base substrate; a functional layer located on a side of the base substrate, a material of the functional layer is a thermal conductive material, and the functional layer includes a first functional portion; an active layer located on a side of the functional layer away from the base substrate, the active layer includes a first active portion including at least one first active sub-portion which is configured to form a channel region of the first transistor; a second conductive layer located on a side of the active layer away from the base substrate, the second conductive layer includes a first conductive portion connected to the first functional portion through a first via hole.