A shift register unit and a driving method thereof, a gate driving circuit, and an array substrate are provided, and the shift register unit includes: an input sub-circuit connected between a signal input terminal and a pull-up node, an output sub-circuit connected between the pull-up node and a signal output terminal; a reset sub-circuit connected between a reset terminal, the pull-up node and the signal output terminal; and a clock signal selection sub-circuit having input terminals connected to a first clock signal terminal and a second clock signal terminal, and a first output terminal connected to the output sub-circuit, and for selecting to provide either a first clock signal or a second clock signal to the output sub-circuit according to voltage levels at the first control terminal and the second control terminal.

A display panel includes a plurality of scan lines and a scan driving circuit for driving the plurality of scan lines, where each of the plurality of scan lines extending in a first direction and sequentially aligned in a second direction, and the first direction intersects with the second direction; the scan driving circuit includes a first scan driving sub-circuit, a second scan driving sub-circuit, and a third scan driving sub-circuit, and the first scan driving sub-circuit is cascaded with the second scan driving sub-circuit; and the display panel includes a first area and a second area adjacent to each other in the second direction, the first scan driving sub-circuit drives scan lines in the first area in a progressive scan mode, and the second scan driving sub-circuit and the third scan driving sub-circuit respectively drive scan lines in the second area in an interlaced scan mode.

Systems, apparatuses, and methods for implementing stripe-based self-gating and change detect signal propagation for retiming pipelines are disclosed. A circuit includes one or more stripes, with each stripe including a plurality of stages of registers, with each stage only receiving input signals from the preceding stage. For a given stripe, the first stage of registers are self-gated to reduce power consumption by only clocking a group of registers when any of their input signals change. The self-gating signals of the first stage of registers are combined together to create a change detect signal which is passed through a register and provided to a second stage of registers as a clock-enable signal. Accordingly, the second stage registers are only clocked when the change detect signal indicates a change will be forwarded from the first stage. This reduces power consumption for the second stage without causing the area increase associated with self-gating circuitry.

A driving method, suitable for a display panel. The display panel includes a first display area, a second display area, a first gate driving circuit and a second gate driving circuit. The second display area comprises an opening. The driving method includes outputting a first gate signal to several first gate lines located at the first display area by the first gate driving circuit; outputting the first gate signal to several second gate lines located at the first display area by the second gate driving circuit, wherein the first gate lines and the second gate lines are arranged in an interlaced manner; outputting the first gate signal and a second gate signal to several third gate lines located at the second display area in the interlaced manner by the first gate driving circuit and the second gate driving circuit.

The present disclosure provides a shift register, a driving circuit, a display device and a driving method for improving the accuracy of an output signal. The first input unit of the shift register is configured to provide a signal at a first fixed potential terminal to a first node, a signal at the input signal terminal to the first node and the signal at the input signal terminal to the first node. A second input unit of the shift register is configured to provide the signal at the input signal terminal to the second node and a signal at the first fixed potential terminal to the second node. An output unit of the shift register is configured to provide a signal at the first clock signal terminal to an output signal terminal of the shift register and a signal at a second fixed potential terminal to the output signal terminal.

A scan driver that includes a plurality of stages of scan driving circuits is provided. Each scan driving circuit includes: a driving transistor, including: a control terminal configured to receive a current-stage scan control signal, a first terminal configured to receive a first clock signal, and a second terminal configured to output a current-stage scan signal; an input stage circuit coupled to the driving transistor, where the input stage circuit includes: a first input transistor and a second input transistor, the first input transistor includes: a control terminal, a first terminal, and a second terminal, the second input transistor includes: a control terminal, a first terminal, and a second terminal, the control terminal of the first input transistor is configured to receive a next-stage scan signal, the control terminal of the second input transistor is configured to receive a previous-stage scan signal, and the second terminal of the first input transistor and the second terminal of the second input transistor are coupled to the control terminal of the driving transistor; a pull-down circuit, coupled to the driving transistor and configured to pull down the current-stage scan control signal and the current-stage scan signal; and a capacitor, coupled to the driving transistor and configured to maintain the current-stage scan control signal, where in a first scan mode, the first terminal of the first input transistor receives the first clock signal, and the first terminal of the second input transistor receives a first scan direction control signal; and in a second scan mode, the first terminal of the first input transistor receives a second scan direction control signal, and the first terminal of the second input transistor receives the first clock signal.

A first flipflop outputs a first signal synchronized with a first clock signal, a second flipflop outputs a second signal synchronized with a second clock signal, and a third flipflop outputs a third signal synchronized with a third clock signal. The second flipflop includes first to fifth transistors. In the first transistor, the second clock signal is input to a first terminal and the second signal is output from a second terminal. In the second transistor, a first signal is input to a first terminal, a second terminal is electrically connected to a gate of the first transistor, and the first clock signal is input to a gate. In the third transistor, the third signal is input to a first terminal, a second terminal is electrically connected to the gate of the first transistor, and the third clock signal is input to a gate.

The present invention provides a liquid crystal display that can reduce occurrence of quality problems and improve adhesive strength between substrates. The present invention is a liquid crystal display including a first substrate, a second substrate, and a seal. The first substrate includes a shift register monolithically formed on an insulating substrate, a plurality of bus lines, a first end, and a display region. The shift register includes a plurality of multistage-connected unit circuits and wiring connected to the plurality of unit circuits, and is arranged in a region between the first end and the display region. At least one of the unit circuits includes a clock terminal, an output terminal, an output transistor, a second transistor, and a bootstrap capacitor. The output transistor and the bootstrap capacitor are arranged in a region between the first end and one of the wiring and the second transistor.

A gate driver of array (GOA) circuit and a display device are disclosed. An n-th sub-circuit in the GOA circuit includes a control module, an output module, a pull-up supplement module, and a leakage switch. The control module is electrically connected to a positive scan control terminal, a negative scan control terminal, an (n2)th scan terminal, an (n+2)th scan terminal, an (n+1)th clock terminal, an (n1)th clock terminal, a high voltage terminal, and a low voltage terminal. The output module is electrically connected to the high voltage terminal, the low voltage terminal, an n-th clock terminal, an n-th scan terminal, and a controllable terminal. The pull-up supplement module includes a supplement switch that is electrically connected to the high voltage terminal, the control module, and the output module. The leakage switch is electrically connected to the control module, the output module, the supplement switch, and the low voltage terminal.

Apparatuses and techniques are described for accessing redundant columns of data in a memory device. To facilitate scaling of a memory device and reduce a clock rate used to access latches of the redundant columns in program and read operations, one or more first-in, first out (FIFO) buffers are provided to output data to, and receive data from, the latches. The FIFO buffers act as an interface between a controller and the latches, and exchange data with the controller at a relatively high clock rate, and exchange data with the latches of the redundant columns at a slower clock rate. During a read operation, the FIFO can prefetch read data from one or more columns and store it until it is needed to replace the data of a defective primary column.