A shift register unit, a method of driving a shift register unit, a gate driving circuit and a touch display device are disclosed. The shift register unit includes a first signal input terminal, a first voltage control terminal, a second signal input terminal, a second voltage control terminal, a signal output terminal, a first voltage terminal, and a second voltage terminal. The shift register unit further comprises a first input circuit, a second input circuit, an output circuit, an anti-leakage circuit, a first control circuit, and a second control circuit. The anti-leakage circuit is configured to bring a first node into conduction with a second node in response to an active potential of the second voltage terminal.

A shift register and a driving method thereof, a gate drive circuit and a display device are provided. The shift register may comprise a transmission sub-circuit, a storage sub-circuit and an output control sub-circuit. The shift register may further comprise an output buffer sub-circuit and a reset sub-circuit. The gate drive circuit may comprise a plurality of cascaded shift registers as described above. The display device may comprise the gate drive circuit. The present disclosure guarantees the working stability, use reliability and display effect of a display panel.

Embodiments of the present disclosure provide a resetting circuit, a shift register, a gate driving circuit and a driving method thereof, and a display device. The first switching sub-circuit, the storage sub-circuit, the controlling sub-circuit, and the second switching sub-circuit in the resetting circuit output a first level signal to a second terminal of the resetting circuit. When a scanning frequency of the gate driving circuit is switched, a resetting function may be implemented by the resetting circuit even if there is no resetting signal provided by a resetting signal terminal for resetting a part of outputting terminals of the gate driving circuit.

A shift register circuit, a gate driving circuit and a method for driving the same, and a display apparatus are disclosed. The shift register circuit includes: an input circuit configured to receive an input signal and output the input signal to a pull-up node; an output circuit configured to receive a clock signal and provide an output signal at a signal output terminal based on the clock signal under control of a level at the pull-up node; a pull-down circuit configured to pull down a level at the signal output terminal under control of a level at a pull-down node; and at least one of a feedback circuit or a pull-down control circuit, wherein the feedback circuit is electrically coupled to the pull-up node, and is configured to output a first feedback signal based on the level at the pull-up node; and the pull-down control circuit is electrically coupled to the pull-up node and the pull-down node, and is configured to receive a second feedback signal and control the level at the pull-down node under control of the level at the pull-up node and the second feedback signal.

Disclosed are a shift register unit, a gate driving circuit, a display apparatus and a driving method. The shift register unit includes: a first input sub-circuit, configured to receive a display input signal from a display input terminal, and input a display output control signal to a first node in a display period of one frame according to the display input signal; a second input sub-circuit, configured to receive a random input signal in the display period of one frame, and input a blanking output control signal to the first node in a blanking period of one frame according to the random input signal; and an output sub-circuit, configured to output a composite output signal via an output terminal under the control of the first node.

According to one aspect of this disclosure, a scanning trigger unit includes a clock signal terminal, a first signal input terminal, a fixed level signal terminal, a first input sub-circuit, an output sub-circuit, a first holding sub-circuit, and a signal output terminal. The first input sub-circuit is connected to the first signal input terminal and a control node, and is configured to provide a first valid signal to the control node; the output sub-circuit is connected to the fixed level signal terminal, the clock signal terminal, and the control node, and is configured to provide a second valid signal to the signal output terminal; and the first holding sub-circuit is connected to the fixed level signal terminal and the signal output terminal, and is configured to hold the second valid signal at the signal output terminal for a predetermined time.

Provided are a display panel and display device. The display panel includes a display area and a non-display area. The display panel further includes multiple cascaded shift registers disposed in the non-display area and multiple scanning lines disposed in the display area. Each shift register is connected to a corresponding scanning line. The shift registers include multiple first shift registers and multiple second shift registers. The first shift registers are capable of unidirectional scanning, and the second shift registers are capable of bidirectional scanning. The display area includes a first display area and a second display area. Each of scanning lines in the first display area are connected to a respective one of the plurality of first shift registers, and each of the at least part of the scanning lines in the second display area are connected to the second shift registers.

Embodiments of the present application provide a shift register unit, a method for driving the same, a gate driving circuit, and a display apparatus. The shift register unit comprises at least two sub-circuits of a first output sub-circuit, a second output sub-circuit, and a third output sub-circuit. The first output sub-circuit is configured to output a voltage at a signal output terminal to a reset signal output terminal; the second output sub-circuit is configured to output the voltage at the signal output terminal to a gating signal output terminal; and the third output sub-circuit is configured to output a voltage at a second voltage terminal to a light-emitting control signal output terminal or is configured to output a voltage at a first voltage terminal to the light-emitting control signal output terminal.

A shift register capable of preventing leakage current and a display device using the same are disclosed. The shift register includes a plurality of stages. Each stage includes a set unit setting a Q node in response to a start pulse or previous output, an inverter for controlling a QB node to have a logic state opposite to that of the Q node, an output unit for outputting any one input clock or a gate off voltage in response to the logic states of the Q and QB nodes, a reset unit including a reset switching element, the reset switching element resetting the Q node with a first reset voltage in response to a reset pulse or next output, and a noise cleaner resetting the Q node with a second reset voltage in response to the QB node. When the reset switching element is turned off, the first reset voltage is greater than a voltage of the reset pulse or the next output for the current.

A shift register circuit that controls back gate voltage of a transistor with a simple configuration and at a low cost, and a display panel. In the shift register circuit, shift registers include: an output circuit, a charge and discharge circuit, a first power supply terminal, and at least one back gate voltage generation circuit. The output circuit or the charge and discharge circuit includes at least one transistor. The back gate voltage generation circuit includes a back gate node. The back gate node is connected to the back gate electrode of the transistor. The back gate voltage generation circuit changes a voltage of the back gate node according to a voltage of a gate electrode of the transistor. The back gate voltage generation circuit is supplied with a drive voltage from the first power supply terminal.