The present disclosure provides a GOA circuit, a method for driving the GOA circuit, and a display panel. The GOA circuit includes a plurality of GOA sub-circuits. Each GOA sub-circuit includes a plurality of cascaded shift register units. Each of the GOA sub-circuits is connected to an independent start signal terminal, and the start signals of different GOA sub-circuits are separated by a time interval for acquisition of touch signals.

A GOA circuit is provided, the GOA circuit being a cascaded multiple-stages GOA circuit, each stage GOA circuit comprising a pull-up control unit, a pull-up unit, a signal downward transfer unit, a pull-down unit, one pull-down maintenance unit and a bootstrap unit, each stage GOA circuit being disposed with a clock signal input terminal, a first node, a first voltage input terminal, a pull-down signal input terminal and a scan signal output terminal to output a scan signal onto a horizontal scan line, the one pull-down maintenance unit comprising an inverter, the first node being disposed between an output terminal of the pull-up control unit and the bootstrap unit, when a potential of the first node is a high potential, a potential of a pull-down signal input to the pull-down signal input terminal is a low potential.

A semiconductor device includes a pre-shift circuit and a shift circuit. The pre-shift circuit shifts an internal write signal by a pre-shift period to generate a pre-write signal. The shift circuit shifts the pre-write signal by a shift period to generate a shift write signal for generating a column selection signal. The column selection signal is activated to select a column path through which data are inputted or outputted. The pre-shift period is set as a period corresponding to a multiple of L times a cycle of a clock signal, wherein L is a natural number which is equal to or greater than two.

A shift register unit and a driving method thereof, a gate driving circuit and a display apparatus. The shift register unit includes an input circuit, a first pull-down circuit, a second pull-down circuit, and an output circuit. In a first state, the first pull-down circuit is configured to pull down the level of a pull-up node, and the second pull-down circuit is configured to pull down a level of the output terminal.

A gate driving circuit includes a plurality of driving stages, wherein an ith (where i is a natural number of 2 or more) driving stage among the plurality of driving stages includes: a output unit outputting an ith output signal including a high voltage generated based on a clock signal in response to a low voltage at a Q-node; a stabilization unit providing the low voltage to the Q-node in response to a switching signal applied to an A-node after the ith output signal is outputted; and an inverter unit outputting the switching signal for controlling the stabilization unit to the A-node.

The present disclosure proposes a shift register circuit and a method for driving the same, a gate driving circuit and a method for driving the same, and a display apparatus. The shift register circuit comprises an input circuit, a reset circuit, a control circuit and a multi-output circuit. The input circuit is configured to receive an input signal and output a signal to a first node based on the input signal; the reset circuit is configured to receive a reset signal and a first reference signal, and output the first reference signal to the first node under control of the reset signal; the control circuit is configured to control a potential at the first node to be an inverted potential of a potential at the second node; and the multi-output circuit is configured to receive the first reference signal and a plurality of clock signals, and output a plurality of driving signals according to the corresponding clock signals and the first reference signal under the control of signals at the first node and the second node.

A shift register circuit and a gate driver including the shift register circuit. The shift register circuit includes an input circuit, a drive circuit, a pull-down circuit, a regulator circuit and a pull-up circuit. The input circuit is configured to receive a first clock signal and is coupled to the first node. The driving circuit is configured to receive the first clock signal and a second clock signal. The input circuit is coupled to the first node. The pull-down circuit is configured to receive the voltage of the first node. The pull-down circuit is coupled to the first node and an output terminal. The pull-down circuit outputs the first voltage to the output terminal in response to the voltage of the first node.

A semiconductor device which shifts a low-level signal is provided. In an example, a first transistor including a first terminal electrically connected to a first wiring and a second terminal electrically connected to a second wiring, a second transistor including a first terminal electrically connected to a third wiring and a second terminal electrically connected to the second wiring, a third transistor including a first terminal electrically connected to a fourth wiring and a second terminal electrically connected to a gate of the second transistor, a fourth transistor including a first terminal electrically connected to a fifth wiring, a second terminal electrically connected to a gate of the third transistor, and a gate electrically connected to a sixth wiring, and a first switch including a first terminal electrically connected to the third wiring and a second terminal electrically connected to a gate of the first transistor are included.

A shift register and a method for driving the same, a gate driving circuit, and a display device, the shift register includes: a pull-up node control circuit allowing a potential of a pull-up node to become high according to a first input signal and a second input signal; a first capacitor coupled between a signal output terminal and the pull-up node of the shift register; a pull-down node control circuit controlling a potential of the pull-down node according to the second clock signal and the third clock signal and the potential of the pull-up node; an output circuit controlling an output of a gate driving signal at the signal output terminal; and a pull-down circuit allowing the potential of the pull-up node and a potential of the signal output terminal to become low.

The present disclosure discloses a gate drive output stage circuit, a gate driving unit, and a drive method. The gate drive output stage circuit includes: a first control sub-circuit configured to transmit a start signal of a compensation driving terminal to a first node; a second control sub-circuit configured to transmit a first clock signal of a first clock terminal to a control node when the first node is at an effective level; a first output sub-circuit configured to transmit a second clock signal of a second clock terminal to a first output terminal when the control node is at an effective level; and a second output sub-circuit configured to transmit a first power supply voltage signal of a first power supply voltage terminal to a second output terminal when the control node is at the effective level.