A shift register circuit according to an embodiment of the present disclosure includes an input sub-circuit and N-stage output sub-circuits. The input sub-circuit is configured to transmit an input signal to a pull up node at a first stage. The output sub-circuit at each stage is configured to transmit a clock signal from a clock signal terminal at a same stage to an output signal terminal at the same stage under the control of a pull-up node at the same stage. The output sub-circuit at each stage is further configured to transmit a signal transmitted to an output signal terminal at the same stage to a pull-up node at an immediately subsequent stage under the control of a shift control signal from a shift control signal terminal at the same stage.

A shift register is disclosed herein. The shift register includes a pull down circuit, a supplementary circuit, an output control circuit, and an input circuit. The supplementary circuit is coupled to the pull down circuit at a first node and a second node and is configured to receive a touch signal. The output control circuit is coupled to the second node. The input circuit is coupled to the first node and is configured to transmit an input voltage to the first node and the second node according to an input signal. The supplementary circuit transmits a voltage value of the touch signal to the second node according to the input voltage and the touch signal, so as to maintain a voltage value of the second node.

The present application provides a shift register unit including: an input sub-circuit coupled to an input terminal, an first voltage terminal and an pull-up node; an output sub-circuit coupled to the pull-up node and art first clock terminal; a first storage sub-circuit having two terminals respectively coupled to the pull-up node and an output terminal; a first reset sub-circuit coupled to an reset terminal, an second voltage terminal, the pull-up node and the output terminal; a second reset sub-circuit coupled to a second clock terminal and a pull-down node; a pull-down sub-circuit coupled to the pull-down node, the second voltage terminal and the output terminal; and a spacing sub-circuit coupled to the pull-up node, the pull-down node and the second voltage terminal. The present application further provides a driving method of a shift register unit, a gate driving circuit and a display device.

A display panel and a display apparatus are provided. The display panel includes a plurality of first signal lines and second signal lines. A display area of the display panel includes first regular display area, second regular display area and an irregularly-shaped display area. The first signal lines disposed in the first and second regular display areas are first and second regular signal lines, respectively. The first signal lines disposed in the irregularly-shaped display area are irregularly-shaped signal lines. At least one irregularly-shaped signal line is a first irregularly-shaped signal line and the other is second irregularly-shaped signal line. A non-display area includes first driving circuit and second driving circuit. The first driving circuit is electrically connected to the first regular signal line and first irregularly-shaped signal line, and the second driving circuit is electrically connected to the second regular signal line and second irregularly-shaped signal line.

An object is to provide a semiconductor device with improved operation. The semiconductor device includes a first transistor, and a second transistor electrically connected to a gate of the first transistor. A first terminal of the first transistor is electrically connected to a first line. A second terminal of the first transistor is electrically connected to a second line. The gate of the first transistor is electrically connected to a first terminal or a second terminal of the second transistor.

Display panel and display device are provided. An exemplary display panel includes a display area and a non-display area surrounding the display area. The display area includes a plurality of gate lines, a plurality of data lines, and an irregularly-shaped edge. The non-display area includes a first non-display area adjacent to the irregularly-shaped edge. The first non-display area includes a first sub-area adjacent to the sub-edge. The plurality of data lines includes a plurality of irregularly-shaped data lines. The plurality of irregularly-shaped data lines includes a plurality of winding portions in the first sub-area which includes at least one first winding portion, and the at least one first winding portion has at least a wiring portion in a film layer different than a remaining portion of the plurality of winding portions.

A drive circuit, a display panel, a display device and a drive method. The drive circuit includes a plurality of shift registers; a first switch circuit connected with the shift registers, which is configured to selectively output output signals of the shift registers or a first voltage based on a first control signal and a second control signal; and a second switch circuit connected with the shift registers, which is configured to selectively output the output signals of the shift registers or the first voltage based on a third control signal and a fourth control signal. A set of shift registers can simultaneously or individually drive two display regions.

A shift register circuit includes a first circuit, M second circuits, and N third circuits. M and N are both positive integers, N is an integer multiple of M, M is greater than or equal to 2, and a quotient of N and M is greater than or equal to 2. The first circuit includes a first signal output terminal. Each second circuit includes a second signal input terminal connected to the first signal output terminal. Each third circuit includes a third signal input terminal that is connected to one of second signal input terminals of the M second circuits. A second signal output terminal of each second circuit is connected to third signal input terminals of N/M third circuits, and different second signal output terminals are connected to different third signal input terminals.

Examples of the present disclosure provide apparatuses and methods related to performing a sort operation in a memory. An example apparatus might include a a first group of memory cells coupled to a first sense line, a second group of memory cells coupled to a second sense line, and a controller configured to control sensing circuitry to sort a first element stored in the first group of memory cells and a second element stored in the second group of memory cells by performing an operation without transferring data via an input/output (I/O) line.

A shift register circuit, a gate driving circuit and a method for driving the same, and a display apparatus are disclosed. The shift register circuit includes: an input circuit configured to receive an input signal and output the input signal to a pull-up node; an output circuit configured to receive a clock signal and provide an output signal at a signal output terminal based on the clock signal under control of a level at the pull-up node; a pull-down circuit configured to pull down a level at the signal output terminal under control of a level at a pull-down node; and at least one of a feedback circuit or a pull-down control circuit, wherein the feedback circuit is electrically coupled to the pull-up node, and is configured to output a first feedback signal based on the level at the pull-up node; and the pull-down control circuit is electrically coupled to the pull-up node and the pull-down node, and is configured to receive a second feedback signal and control the level at the pull-down node under control of the level at the pull-up node and the second feedback signal.