A marching memory is disclosed having an array of memory units. Each memory unit has a sequence of bit level cells. Each bit-level cell has a transfer-transistor having a first main-electrode connected to a clock signal supply line through a first delay element, and a control-electrode connected to an output terminal of a first neighboring bit-level cell positioned at an input side of the array of the memory units, through a second delay element. Each bit-level cell also has a reset-transistor having a first main-electrode connected to a second main-electrode of the transfer-transistor, a control-electrode connected to the clock signal supply line, and a second main-electrode connected to the ground potential. Each bit-level cell also has a capacitor connected in parallel with the reset-transistor.

There are provided a shift register unit and a driving method thereof. The shift register unit includes: an input circuit, whose first terminal receives an input signal of the shift register unit, and second terminal is connected to a pull-up node, the input circuit being configured to output the input signal to the pull-up node; an output circuit, whose first terminal is connected to a clock signal terminal, second terminal is connected to the pull-up node, third terminal is connected to an output terminal of the shift register unit, the output circuit being configured to output a signal of the clock signal terminal to the output terminal under the control of the pull-up node; a pull-up node control circuit, and the pull-up node control circuit being configured to discharge the pull-up node through third power supply voltage terminal under the control of a first power supply voltage terminal.

A shift register includes a pull-up node, a pull-down node and a compensation sub-circuit. The pull-up node is configured to control a signal output terminal of the shift register to output a gate scanning signal, and the pull-down node is configured to stop the signal output terminal of the shift register from outputting the gate scanning signal. The compensation sub-circuit is connected to the pull-up node and/or the pull-down node, a compensation signal terminal, and a common voltage terminal. The compensation sub-circuit is configured to output a voltage from the compensation signal terminal to an output terminal of the compensation sub-circuit under the control of a signal from the pull-up node and/or a signal from the pull-down node. The output terminal of the compensation sub-circuit is connected to the common voltage terminal.

According to an embodiment, a semiconductor device includes a plurality of first interconnections, a plurality of gate dielectric films, and a plurality of second interconnections. The plurality of first interconnections are oxide semiconductors formed in parallel at predetermined intervals in a first direction. The plurality of gate dielectric films are formed on surfaces of the first interconnections, respectively. The plurality of second interconnections are conductors formed at predetermined intervals in parallel to a second direction orthogonal to the first direction, respectively, to bridge over the gate dielectric films.

A display device with a variant-shape display region other than the rectangular display region is configured to form a scanning line drive circuit along the variant-shape display region. The scanning line drive circuit includes bus wiring group with clock wiring for supplying clocks with three or more phases and the power supply wiring for supplying power, and the unit circuits for configuring the shift register including five or more transistors. The bus wiring and the unit circuits are formed on the different regions so as not to cross with one another.

A memory device is provided. The memory device includes a shift register array having a plurality of shift registers arranged in a matrix of a plurality of rows and a plurality of columns. Each of the plurality of rows comprises a first plurality of shift registers and each of the plurality of columns comprises a second plurality of shift registers. Each of the plurality of rows are associated with a read word line and a write word lines. Each of the plurality of rows are associated with a data input line and a data output line. Each of the plurality of shift arrays comprises a static random access memory.

A display panel includes a display area, a non-display area surrounding the display area, and a plurality of signal lines, signal connection lines, and cascaded shift registers aligned in the non-display area. The display area includes a curved corner, and the non-display area includes a corner non-display area adjacent to the curved corner. The cascaded shift registers are electrically connected by associated cascade lines, and each cascaded shift register is connected with a corresponding signal line through an associated signal connection line. The associated cascade lines are located on a side of the cascaded shift registers away from the display area, and the signal lines are located on a side of the associated cascade lines away from the cascaded shift registers. The wiring directions of the signal lines and the extension lines of the associated cascade lines are in parallel with an outer edge of the non-display area.

Apparatuses including a first-in first-out circuit are described. An example apparatus includes: a first-in first-out circuit including a first latch, a second latch and a logic circuit coupled in series. The first latch receives first data and latches the first data responsive to a first input pointer signal. The second latch receives the latched first data from the first latch and latches the received first data responsive to a second input pointer signal that has a different phase from the first input pointer signal and thus provides a second data. The logic circuit receives the second data and an output pointer signal and further provides an output data responsive to the output pointer signal.

Provided is a technique of causing less display irregularities to occur when the scanning of the gate lines is resumed in a display device in which the scanning of gate lines is performed intermittently. A display device includes a display panel, and a driving circuitry that includes a plurality of drive circuits for scanning gate lines. The driving circuitry alternately switches a scanning period in which the gate lines are scanned, and a non-scanning period in which the scanning of the gate lines is suspended, during one vertical scanning period, according to a control signal. Each driving circuit 301n includes a first switching element N that applies a selection voltage to the gate line; an internal line netA; a second switching element A that charges the internal line netA to a first potential; and a third switching element B that includes a drain electrode connected to the internal line netA, and a source electrode having a second potential that is lower than the first potential. a drive circuit corresponding one of the gate lines that is selected at start of the scanning period includes a charging circuit 301b(n) which recharges the internal line netA of this drive circuit to a potential equal to or higher than the first potential, before the start of this scanning period.

Display panel and display device are provided. The display panel includes scan lines and a scan driving circuit including shift registers in a cascaded configuration and multiplexers. One shift register is connected to one multiplexer. One multiplexer is connected to M scan lines and includes M control units connected with the scan lines in a one-to-one correspondence. Output terminals of switch branches in a control unit are connected to one scan line. An input terminal of a main switch branch is connected to an output terminal of the shift register. An input terminal of an auxiliary switch branch is connected to a first signal line. In one scanning period, in M consecutive time stages, a signal from each shift register to the multiplexer includes effective voltage levels; the main switch branches in the control units are switched on sequentially, and output the scanning signal to the M scan lines sequentially.