A transistor whose channel region includes an oxide semiconductor is used as a pull down transistor. The band gap of the oxide semiconductor is 2.0 eV or more, preferably 2.5 eV or more, more preferably 3.0 eV or more. Thus, hot carrier degradation in the transistor can be suppressed. Accordingly, the circuit size of the semiconductor device including the pull down transistor can be made small. Further, a gate of a pull up transistor is made to be in a floating state by switching of on/off of the transistor whose channel region includes an oxide semiconductor. Note that when the oxide semiconductor is highly purified, the off-state current of the transistor can be 1 aA/m (110.sup.18 A/m) or less. Therefore, the drive capability of the semiconductor device can be improved.

A shift register includes a forward/backward scan-control module, configured to transmit a signal of a forward-scan-signal terminal or a signal of a backward-scan-signal terminal to a first node; an interlock module, configured to transmit a signal of a first voltage terminal to a second node, and transmit a signal of a second voltage terminal to the first node; a pull-down module, configured to transmit the signal of the first voltage terminal to a gate-signal output terminal; an output module, configured to transmit a signal of a second clock-signal terminal to the gate-signal output terminal; and a reset module, configured to transmit the signal of the second voltage terminal to the first node, and transmit the signal of the first voltage terminal to the gate-signal output terminal. The disclosed shift register can prevent leakage of the first node, and thus improve the quality and the performance of the shift register.

A shift register includes a forward/backward scan-control module, configured to transmit a signal of a forward-scan-signal terminal or a signal of a backward-scan-signal terminal to a first node; an interlock module, configured to transmit a signal of a first voltage terminal to a second node, and transmit a signal of a second voltage terminal to the first node; a pull-down module, configured to transmit the signal of the first voltage terminal to a gate-signal output terminal; an output module, configured to transmit a signal of a second clock-signal terminal to the gate-signal output terminal; and a reset module, configured to transmit the signal of the second voltage terminal to the first node, and transmit the signal of the first voltage terminal to the gate-signal output terminal. The disclosed shift register can prevent leakage of the first node, and thus improve the quality and the performance of the shift register.

A shift register unit, a drive method, a gate drive circuit and a display device are provided, in the field of display technologies. A first input signal terminal connected to an input control circuit of the shift register unit is connected to a first output terminal of a shift register unit at a previous stage, and a second input signal terminal connected to the input control circuit is connected to a second output terminal of the shift register unit at the previous stage. A signal output by the first output terminal of the shift register unit at the previous stage is a first clock signal and a signal output by the second output terminal is a second clock signal. Therefore, the first control node of the shift register unit may be controlled by flexibly adjusting a timing sequence of the first clock signal and the second clock signal.

A shift register and driving method thereof, a gate driving circuit and a display apparatus are provided. The shift register includes an input unit, a reset unit, a first control unit, a second control unit, a first output unit, a second output unit, a first signal output end and a second signal output end. Potential of the first signal output end is controlled by use of the input unit, the reset unit, the first control unit and the first output unit, and potential of the second signal output end is controlled by use of the input unit, the reset unit, the second control unit and the second output unit. The first control unit and the first output unit, the second control unit and the second output unit are utilized for controlling and sharing the input unit and the reset unit so that function of two shift register units are realized.

A shift register, gate drive circuit and display panel are provided. The shift register includes a latch unit, a NAND gate unit, a buffer unit and a switch unit. The latch unit, the NAND gate unit and the buffer unit are configured to produce a scanning driving signal and a scanning stopping signal. The latch unit is configured to control the switch unit to be turned on so as to output the scanning driving signal or the scanning stopping signal from the output terminal of the shift register, or control the switch unit to be turned off so as to enable the output terminal of the shift register to float.

Provided are an organic light-emitting display panel and an organic display device, the organic light-emitting display panel includes: a display region and at least one peripheral circuit region; the peripheral circuit region is provided with shift registers cascaded in stages and clock signal lines of at least two different types, the number of clock signal lines in at least one of the different types is not less than 2, clock signals of one type of the clock signal lines are the same, clock signals of different types of the clock signal lines are different; the clock signal lines each is electrically connected to a clock signal input terminal of one of the shift registers, the shift registers each is configured to output a gate driving signal according to the clock signal in the clock signal line electrically connected to the input terminal of one of the shift registers.

Array substrate, display panel and display device are provided. The array substrate includes multiple scanning lines, multiple data lines, multiple shift registers and multiple switching units. Each shift register is used for inputting a scanning signal to one terminal of a corresponding scanning line, the other terminal of each scanning line is connected with a first terminal of the switching unit, a second terminal of the switching unit receives a first reference voltage, a control terminal of the switching unit receives a first control signal. The shift register and the switching unit simultaneously pull down a voltage level of the scanning line to a low level. The present invention can realize a narrow frame, increase the user experience and ensure that the time that the voltage level of the scanning line pulled to the low level is the same.

The present disclosure discloses a gate drive output stage circuit, a gate driving unit, and a drive method. The gate drive output stage circuit includes: a first control sub-circuit configured to transmit a start signal of a compensation driving terminal to a first node; a second control sub-circuit configured to transmit a first clock signal of a first clock terminal to a control node when the first node is at an effective level; a first output sub-circuit configured to transmit a second clock signal of a second clock terminal to a first output terminal when the control node is at an effective level; and a second output sub-circuit configured to transmit a first power supply voltage signal of a first power supply voltage terminal to a second output terminal when the control node is at the effective level.

A shift register and a method for driving the same, a gate driving circuit and a display apparatus are disclosed. The shift register includes: an input circuit configured to transmit an input signal from an input terminal to a first node; a first node control circuit configured to transmit a first voltage signal from a first voltage signal terminal to the first node; a second node control circuit configured to transmit a first clock signal from a first clock signal terminal to a second node; a third node control circuit configured to transmit a second voltage signal from a second voltage signal terminal to a third node; and an output circuit configured to transmit one of the first voltage signal from the first voltage signal terminal or the second voltage signal from the second voltage signal terminal to an output terminal.