A gate on array (GOA) unit, a gate driver circuit, and a display device are provided. The GOA unit includes a driver circuit, a pull-down circuit, and a pull-down control circuit, the driver circuit is configured to output a first signal from an output end of the GOA unit. The pull-down circuit is connected with the driver circuit and at least one voltage end that provides a voltage signal, the pull-down circuit is configured to input the voltage signal into a control end of the driver circuit to drive the driver circuit to be in an off state when the GOA unit outputs an off signal. The pull-down control circuit is connected with the pull-down circuit and the driver circuit, and is configured to control the pull-down circuit to input the voltage signal to the control end of the driver circuit.

A marching memory is disclosed having an array of memory units. Each memory unit has a sequence of bit level cells. Each bit-level cell has a transfer-transistor having a first main-electrode connected to a clock signal supply line through a first delay element, and a control-electrode connected to an output terminal of a first neighboring bit-level cell positioned at an input side of the array of the memory units, through a second delay element. Each bit-level cell also has a reset-transistor having a first main-electrode connected to a second main-electrode of the transfer-transistor, a control-electrode connected to the clock signal supply line, and a second main-electrode connected to the ground potential. Each bit-level cell also has a capacitor connected in parallel with the reset-transistor.

A shift register unit, drive method thereof, gate drive device and display device. The shift register unit includes: an input subcircuit; a reset subcircuit; an output subcircuit configured to provide a clock signal at a clock signal end to a current stage shift register unit output end in response to a voltage signal at the pull-up node and a control signal having a first voltage level, and to disable an output at the current stage output end in response to the control signal having a second voltage level; a pull down control subcircuit configured to provide a second voltage signal having a low voltage level to a pull-down node in response to the voltage signal at the pull-up node, and to provide the voltage signal having a high voltage level to the pull-down node in response to the voltage signal having a high voltage level; and a pull down subcircuit.

A gate driver and a touch display apparatus thereof are provided. The gate driver includes a plurality of shift registers and at least one loop circuit. The shift registers provide multiple gate signals to a touch display module. The loop circuit is coupled in series with the shift registers and receives at least one touch switching signal to set a loop time of the loop circuit. The touch display module performs at least one touch scan during the loop time.

According to one embodiment, a sensor including a first drive electrode, a second drive electrode disposed to be adjacent to the first drive electrode, a third drive electrode disposed to be adjacent to the second drive electrode, a first shift register circuit connected to the first drive electrode, a second shift register circuit connected to the first shift register circuit and the third drive electrode, and an OR circuit connected to the second drive electrode, the first shift register circuit, and the second shift register circuit.

A shift register, a method for driving the same, a gate drive circuitry and a display apparatus are provided. The shift register includes: an input circuit, connected to a signal input terminal, a pull-up node and a first control terminal, and configured to provide a signal of the signal input terminal to the pull-up node under the control of the first control terminal; an output circuit, connected to the pull-up node, a first clock signal terminal and a signal output terminal, and configured to provide a signal of the first clock signal terminal to the signal output terminal under the control of the pull-up node; and a pull-up node control circuit, connected to the pull-up node, a second clock signal terminal, a third clock signal terminal and a first voltage terminal, and configured to provide a signal of the first voltage terminal to the pull-up node.

The present disclosure relates to the field of display technologies and, more particularly, to a shift register unit, a shift register circuit, and a display device. The shift register unit includes a detection input circuit, a display input circuit, an inverter circuit, a pull-down circuit, a reset circuit, and a first output circuit. In a working process of the shift register unit, the display input circuit and the detection input circuit share the inverter circuit, the pull-down circuit, the reset circuit, and the first output circuit.

A shift register circuit includes a first output sub-circuit, and a second output sub-circuit. The first output sub-circuit is coupled to a clock signal terminal, a control signal terminal, a pull-up node and an output signal terminal, and is configured to output a clock signal output via the clock signal terminal to the output signal terminal under control of the control signal output via a control signal terminal and the potential of the pull-up node. The second output sub-circuit is coupled to the clock signal terminal, the pull-up node and the output signal terminal, and is configured to output the clock signal to the output signal terminal under control of the potential of the pull-up node.

An array substrate, a manufacturing method thereof and a display panel are provided. The array substrate includes a base substrate, a plurality of thin film transistors and a first light shielding layer. The base substrate includes a first surface and a second surface respectively located on opposite sides of the base substrate. The plurality of thin film transistors are disposed on the first surface of the base substrate, and each of the plurality of thin film transistors includes an active layer. The first light shielding layer is disposed on the second surface of the base substrate. The first light shielding layer has at least one opening that overlaps with at least one thin film transistor in a direction perpendicular to the second surface of the base substrate to allow light to irradiate at least the active layer of at least one thin film transistor.

A gate driving circuit includes M levels of shift registers. Each level of shift register includes a first register unit and a second register unit. The first register units of the M levels of shift registers are connected to each other in a cascaded manner, the second register units of the M levels of shift registers are connected to each other in a cascaded manner, and an output end of the first register unit and an output end of the second register unit of each level of shift register are electrically connected to an output end of the level of shift register, where M is a positive integer greater than or equal to 1.