A display device with a variant-shape display region other than the rectangular display region is configured to form a scanning line drive circuit, along the variant-shape display region. The scanning line drive circuit includes bus wiring group with clock wiring for supplying clocks with three or more phases and the power supply wring for supplying power, and the unit circuits for configuring the shift register including five or more transistors. The bus wiring and the unit circuits are formed on the different regions so as not to cross with one another.

Disclosed are a shift register unit, a gate driving circuit, a display apparatus and a driving method. The shift register unit includes: a first input sub-circuit, configured to receive a display input signal from a display input terminal, and input a display output control signal to a first node in a display period of one frame according to the display input signal; a second input sub-circuit, configured to receive a random input signal in the display period of one frame, and input a blanking output control signal to the first node in a blanking period of one frame according to the random input signal; and an output sub-circuit, configured to output a composite output signal via an output terminal under the control of the first node.

A gate driver of array (GOA) circuit and a display device are disclosed. An n-th sub-circuit in the GOA circuit includes a control module, an output module, a pull-up supplement module, and a leakage switch. The control module is electrically connected to a positive scan control terminal, a negative scan control terminal, an (n2)th scan terminal, an (n+2)th scan terminal, an (n+1)th clock terminal, an (n1)th clock terminal, a high voltage terminal, and a low voltage terminal. The output module is electrically connected to the high voltage terminal, the low voltage terminal, an n-th clock terminal, an n-th scan terminal, and a controllable terminal. The pull-up supplement module includes a supplement switch that is electrically connected to the high voltage terminal, the control module, and the output module. The leakage switch is electrically connected to the control module, the output module, the supplement switch, and the low voltage terminal.

A shift register unit includes an input module, a first output module, a first pull-down module, a reset module, and a leakage-proof module. The input module is coupled to a pull-up node, a control signal terminal, and an input signal terminal. The first output module is coupled to the pull-up node, a first output terminal, and a second clock signal terminal. The first pull-down module is coupled to the first output terminal, a first signal terminal, and a first clock signal terminal. The reset module is coupled to a reset signal terminal, the pull-up node, and the first output terminal. The leakage-proof module is coupled to a second signal terminal, the first node, and the pull-up node.

A gate drive circuit, a display device and a driving method are provided. The gate drive circuit includes a scan signal generation circuit and output control circuits in N stages. The scan signal generation circuit includes first output terminals in 2N stages, and is configured to output scan pulse signals in an order at the first output terminals in 2N stages; each of the output control circuits in N stages includes an input terminal, a first control terminal, a second control terminal, a second output terminal, and a bootstrap circuit, and is configured to control the bootstrap circuit, under control of a first control signal received by the first control terminal, an input signal received by the input terminal, and a second control signal received by the second control terminal, to output an output pulse signal with different pulse levels at the second output terminal.

A gate drive circuit, a method of driving a gate drive circuit, a display device, and a method of manufacturing an array substrate are provided. The gate drive circuit includes a repair signal line, a plurality of output signal lines, and a plurality of shift register units that are cascaded. The repair signal line is configured to transmit the repair signal to the first output signal line. The plurality of shift register units include a first shift register unit and a plurality of second shift register units, and the plurality of second shift register units are correspondingly connected to the second output signal lines. The first output signal line corresponds to but is in a state of being disconnected to the first shift register unit, and the first output signal line and the plurality of second output signal lines are configured to output a set of shift pulse signals.

A shift register unit, a gate driving circuit, a display device and a driving method are provided. The shift register unit includes an input circuit, an output circuit, a first reset circuit, a second reset circuit and a common reset circuit. The input circuit is configured to control a level of a first node in response to an input signal; the output circuit includes an output terminal and is configured to output an output voltage signal to the output terminal under control of the level of the first node; the common reset circuit includes a reset control terminal and is configured to reset the first node when a reset turn-on signal is input to the reset control terminal; and the first reset circuit is configured to provide the reset turn-on signal to the reset control terminal in response to a first reset signal.

The embodiments of the present disclosure disclose a gate driving circuit and a display panel. In the gate driving circuit, a control unit of a shift register may input a dual pulse control signal to a first control terminal of an output unit; and the output unit outputs a scanning signal having a pulse width equal to a pulse period of the dual pulse control signal to a corresponding gate line under the control of the dual pulse control signal. In this way, the output unit is controlled by the control unit to output a scanning signal of which a pulse width may be modulated, so as to output a gate signal of which a pulse width may be modulated.

The present application provides a shift register and a method of driving the same, and a gate driving circuit. The shift register includes a detection sub-shift register. The detection sub-shift register includes: a detection input sub-circuit configured to provide a signal of the first input terminal to the pull-up control node under the control of the first clock signal terminal, and provide a signal of the second clock signal terminal to the first pull-up node under the control of the pull-up control node; and a detection output sub-circuit configured to provide a signal of the third clock signal terminal to the first output terminal under the control of the first pull-up node.

A shift register unit and a method for driving the same, a gate driving circuit, and a display apparatus are disclosed. The shift register unit includes: an input circuit configured to transmit an input signal to a pull-up node; an output circuit configured to transmit a clock signal to an output signal terminal under control of a voltage at the pull-up node; a first reset circuit configured to reset the pull-up node to a first level under control of a first reset signal; a first pull-down control circuit configured to control levels at the pull-up node and the output signal terminal under control of a first control signal; and a first voltage control circuit electrically connected to a second control signal terminal, and configured to control a voltage signal waveform at the first pull-down node under control of a second control signal.