A GOA circuit is provided, the GOA circuit being a cascaded multiple-stages GOA circuit, each stage GOA circuit comprising a pull-up control unit, a pull-up unit, a signal downward transfer unit, a pull-down unit, one pull-down maintenance unit and a bootstrap unit, each stage GOA circuit being disposed with a clock signal input terminal, a first node, a first voltage input terminal, a pull-down signal input terminal and a scan signal output terminal to output a scan signal onto a horizontal scan line, the one pull-down maintenance unit comprising an inverter, the first node being disposed between an output terminal of the pull-up control unit and the bootstrap unit, when a potential of the first node is a high potential, a potential of a pull-down signal input to the pull-down signal input terminal is a low potential.

A shift register circuit includes a set circuit, a first reset circuit, a first control circuit, and an output circuit. The output circuit is configured to change an active potential at the first node further away from an inactive potential in response to a first clock signal transferred to a signal output terminal being active, and the first control circuit is further configured to, responsive to the first clock signal transferred to the signal output terminal being active, restrict a change in the active potential at the first node based on a second reference voltage from a second reference voltage, the second reference voltage having a magnitude between an active input pulse and the inactive potential.

In a method of using an ultrasonic sensor comprising a two-dimensional array of ultrasonic transducers, a plurality of ultrasonic signals are transmitted according to a beamforming pattern at a position of the two-dimensional array. The beamforming pattern focuses the plurality of ultrasonic signals to location above the two-dimensional array, wherein the beamforming pattern identifies ultrasonic transducers of the two-dimensional array that are activated during transmission of the ultrasonic signals, and wherein at least some ultrasonic transducers of the beamforming pattern are phase delayed with respect to other ultrasonic transducers of the beamforming pattern. At least one reflected ultrasonic signal is received at the position according to a receive pattern, wherein the receive pattern identifies at least one ultrasonic transducers of the two-dimensional array that is activated during the receiving. The transmitting and the receiving are repeated at a plurality of positions of the two-dimensional array.

A shift register circuit includes a first output sub-circuit, and a second output sub-circuit. The first output sub-circuit is coupled to a clock signal terminal, a control signal terminal, a pull-up node and an output signal terminal, and is configured to output a clock signal output via the clock signal terminal to the output signal terminal under control of the control signal output via a control signal terminal and the potential of the pull-up node. The second output sub-circuit is coupled to the clock signal terminal, the pull-up node and the output signal terminal, and is configured to output the clock signal to the output signal terminal under control of the potential of the pull-up node.

According to one embodiment, an arithmetic device includes one or a plurality of arithmetic units. One of the one or plurality of arithmetic units includes a memory part including a plurality of memory regions, and an arithmetic part. At least one of the memory regions includes a memory element. The memory element is of a shift register-type.

A shift register unit includes a common circuit and an output circuit. The common circuit is configured to control a potential at a pull-up node under the control of an input end, a resetting end and a first clock signal input end. The output circuit is configured to control 2M gate driving signal output ends to output gate driving signals respectively under the control of the pull-up node, a noise reduction control end and an output control end, where M is an integer greater than 1.

An electronic device includes clock generation circuitry. The clock generation circuitry includes a first flip flop receiving as input a device clock and being triggered by an input clock and a second flip flop receiving, as input, output from the first flip flop and being triggered by the input clock. A first inverter receives output from the first flip flop as input and a second inverter receives output from the second flip flop as input. A first AND gate receives, as input, output from the second flip flop and the first inverter, and generates a first clock as output. A second AND gate receives, as input, output from the first flip flop and the second inverter, and generates a second clock as output.

Provided are a display panel and display device. The display panel includes a display area and a non-display area. The display panel further includes multiple cascaded shift registers disposed in the non-display area and multiple scanning lines disposed in the display area. Each shift register is connected to a corresponding scanning line. The shift registers include multiple first shift registers and multiple second shift registers. The first shift registers are capable of unidirectional scanning, and the second shift registers are capable of bidirectional scanning. The display area includes a first display area and a second display area. Each of scanning lines in the first display area are connected to a respective one of the plurality of first shift registers, and each of the at least part of the scanning lines in the second display area are connected to the second shift registers.

The present embodiment of the invention provides a gate driving circuit and a display apparatus using the gate driving circuit. The gate driving circuit has a plurality of shift registers, and each shift register includes a first output unit, a first pull-down unit, a second output unit, a second pull-down unit, a voltage coupling unit, and a voltage boosting unit. The first output unit is coupled to a node and a first output end. The second output unit is coupled to the node and a second output end. The first pull-down unit is coupled to the first output end and a reference potential. The second pull-down unit is coupled to the second output end and the reference potential. The voltage coupling unit is coupled between the node and the second output end. The voltage boosting unit is coupled to a preset potential, the first output end, and a node and a gate high potential of a shift register at a previous stage.

A shift register includes an input sub-circuit, a first noise reduction sub-circuit, and a first pull-down sub-circuit. The first noise reduction sub-circuit is coupled to the pull-up node, the first pull-down node and a first voltage signal terminal, and is configured to transmit a first voltage signal to the pull-up node under control of the first pull-down node; the input sub-circuit is coupled to the pull-up node and a signal input terminal, and is configured to transmit an input signal to the pull-up node in response to the input signal; the first pull-down sub-circuit is coupled to the signal input terminal, the first pull-down node and the first voltage signal terminal, and is configured to transmit the first voltage signal to the first pull-down node in response to the input signal, so that the first noise reduction sub-circuit stops transmitting the first voltage signal to the pull-up node.