A display device with a variant-shape display region other than the rectangular display region is configured to form a scanning line drive circuit along the variant-shape display region. The scanning line drive circuit includes bus wiring group with clock wiring for supplying clocks with three or more phases and the power supply wiring for supplying power, and the unit circuits for configuring the shift register including five or more transistors. The bus wiring and the unit circuits are formed on the different regions so as not to cross with one another.

The disclosure discloses a shift register, a gate drive circuit, a driving method thereof, and a display device, and the shift register includes: an input sub-circuit, an output sub-circuit, and an output control sub-circuit, where the input sub-circuit is configured to provide a signal of a first reference voltage signal terminal to a pull-up node under control of an input signal terminal; the output sub-circuit is configured to provide a signal of a clock signal terminal to a first signal output terminal under control of a potential of the pull-up node; and the output control sub-circuit is configured to provide a signal of the first signal output terminal to a second signal output terminal under joint control of an output control signal terminal, a third reference voltage signal terminal, and a fourth reference voltage signal terminal.

Display panel and display device are provided. The display panel includes scan lines and a scan driving circuit including shift registers in a cascaded configuration and multiplexers. One shift register is connected to one multiplexer. One multiplexer is connected to M scan lines and includes M control units connected with the scan lines in a one-to-one correspondence. Output terminals of switch branches in a control unit are connected to one scan line. An input terminal of a main switch branch is connected to an output terminal of the shift register. An input terminal of an auxiliary switch branch is connected to a first signal line. In one scanning period, in M consecutive time stages, a signal from each shift register to the multiplexer includes effective voltage levels; the main switch branches in the control units are switched on sequentially, and output the scanning signal to the M scan lines sequentially.

Embodiments of the present disclosure provide a shift register circuitry and a driving method thereof, a gate driving circuitry, and a display device. The shift register circuitry includes an input circuit and a plurality of output circuits coupled to the input circuit. The input circuit is coupled to an input signal terminal, and is configured to, under the control of the voltage at the input signal terminal, cause the plurality of output circuits to operate. Each of the plurality of output circuits is coupled to a respective clock signal terminal and a respective output signal terminal, and is configured to operate to couple the clock signal terminal to the output signal terminal so as to output a driving signal at the output signal terminal.

The present disclosure provides a gate driving circuit, a method of driving a gate driving circuit, and a display panel. The gate driving circuit includes a plurality of driving units connected in cascade. Each driving unit includes: N shift register units; and a mode control circuit connected to the N shift register units, wherein the mode control circuit is configured to receive a control signal for the driving unit, and connect the N shift register units in one of a plurality of resolution modes under the control of the control signal.

A display substrate, includes: a display region. The display region includes a plurality of sub-pixels disposed on a substrate, a plurality of first signal lines extending in a first direction, and a plurality of data lines extending in a second direction. At least one sub-pixel includes a driving circuit, and the driving circuit includes a plurality of transistors and at least one storage capacitor. The transistor at least includes a first conductive layer and a second conductive layer. The plurality of first signal lines is located in a third conductive layer. The third conductive layer is located on a side of a control electrode of a transistor of the driving circuit away from the substrate.

The present invention provides a liquid crystal display that can reduce occurrence of quality problems and improve adhesive strength between substrates. The present invention is a liquid crystal display including a first substrate, a second substrate, and a seal. The first substrate includes a shift register monolithically formed on an insulating substrate, a plurality of bus lines, a first end, and a display region. The shift register includes a plurality of multistage-connected unit circuits and wiring connected to the plurality of unit circuits, and is arranged in a region between the first end and the display region. At least one of the unit circuits includes a clock terminal, an output terminal, an output transistor, a second transistor, and a bootstrap capacitor. The output transistor and the bootstrap capacitor are arranged in a region between the first end and one of the wiring and the second transistor.

A shift register circuit includes a first control sub-circuit and a first output sub-circuit. The first control sub-circuit is configured to: adjust a voltage of a first node to a turn-on voltage due to an influence of a first direct current voltage signal from a first clock signal terminal, an initial voltage signal from an initial signal terminal and a second direct current voltage signal from a second clock signal terminal; and maintain the voltage of the first node at the turn-on voltage due to an influence of a first clock signal from the first clock signal terminal and a second clock signal from the second clock signal terminal. The first output sub-circuit is configured to be turned on under a control of the turn-on voltage of the first node to transmit a first voltage signal from a first voltage terminal to a signal output terminal.

The present disclosure relates to a shiftable memory comprising: a plurality of memory cells arranged in rows and columns, wherein the memory cells of the rows are interconnected, thereby forming chains of memory cells; at least one first serial output data port; output data logic for connecting an output of any of the chains of memory cells to the first serial output data port, or at least one first parallel output data port and at least one read shift register configured for serially collecting serial output data from the output of any of the chains of memory cells; and/or at least one first serial input data port; input data logic for connecting the first serial input data port to an input of any of the chains of memory cells, or at least one parallel input data port and at least one write shift register for serially shifting input data to the input of any of the chains of memory cells; and a controller configured to control the shifting of the data in the chains of memory cells, the controller further configured to control the output data logic and/or the input data logic. The disclosure further relates to a method for operating the shiftable memory.

A gate driving circuit includes a plurality of stages connected to one another, wherein each of the plurality of stages includes an output unit which outputs a first clock signal as a gate voltage in accordance with a voltage of a Q node and a voltage of a QB node; a first node control unit which controls the voltage of the Q node; and a second node control unit which controls the QB node, wherein the first node control unit includes second and third transistors which discharge the Q node, the second transistor outputs a ground voltage to the Q node in response to a second clock signal, and the third transistor outputs the ground voltage to the Q node in response to the voltage of the QB node.