A gate driving circuit and a display panel with the gate driving circuit are provided. The gate driving circuit includes shift registers for providing scan signals to gate lines of the display panel. Each shift register includes a main circuit and a discharge circuit. In the main circuit, a pre-charge unit is coupled to a first node and is configured to output a pre-charge signal to the first node, a pull-up unit is coupled to the first node and a second node and is configured to output an m.sup.th stage scan signal of the 1.sup.st to N.sup.th stage scan signals to the second node; and a reset unit is coupled to the first node and is configured to receive a reset signal. In the discharge circuit, a pull-down unit is coupled to the first node and the second node and is configured to receive a pull-down control signal.

Provided are a display panel and display device. The display panel includes a driver circuit comprising a shift register that is N-stage cascaded, wherein N is a number greater than or equal to 2; where the shift register comprises: a third control unit configured to receive a first voltage signal and generate an output signal in response to a signal of a third node, or receive a second voltage signal and generate an output signal in response to a signal of a second node; and a fourth control unit comprising a first capacitor, a first transistor and a second transistor, where a second plate of the first capacitor is connected to a drain of the first transistor, a source of the second transistor is connected to a first node, and a drain of the second transistor is connected to the third node.

According to the embodiments of the disclosure, a shift register and a method for driving the same, a gate driving circuit and a display apparatus may be provided. The shift register includes an input module, a node control module, a first output module and a second output module. The input module may control a potential at a first node via an input signal end and a first clock signal end, the node control module may configured to control the potential at a first node via a first control signal end and a DC signal end, the first output module may control the potential at a driving signal output end via a second control signal end and the DC signal end, and the second output module may maintain a voltage difference between the first node and the driving signal output end in a stable state when the first node is in a floating state and control the potential at the driving signal output end via the first node and the second clock signal end. By cooperating with each other, these four modules may achieve the outputs of scanning signals with a simpler structure and a fewer signal lines, so as to simplify the manufacturing process and reduce the production cost.

A shift register includes a first input sub-circuit configured to transfer a first input signal at a first input terminal to a first node in response to a first scan signal at a first scan terminal being active, a first level control sub-circuit configured to transfer a first power supply voltage at a first power supply terminal to a first output control node and a second output control node in response to the first node being at an active potential, and an output sub-circuit configured to transfer a first clock signal at a first clock terminal to a first output in response to the first output control node being at an active potential, and to transfer a second clock signal at a second clock terminal to a second output terminal in response to the second output control node being at an active potential.

The present disclosure provides a shift register. The shift register includes: a first node control module for controlling level at the first node; a second node control module for controlling level at a second node; and an output control module for controlling the output terminal to output high or low level. The first node control module includes an input unit configured to write the input signal into the third node and a protection unit configured to control a level at a fourth node based on a level at the third node and control writing of the level at the fourth node into the first node based on the second clock signal. The technical solution of the present disclosure can prevent the transistor for providing the third node with inputting signal from being broken down.

A shift register, a driving circuit and a display device are provided. The shift register comprises an output circuit, a node control circuit, and a first node charging circuit. The output circuit provides a signal at a first clock signal terminal or a signal at a first reference voltage terminal to a gate signal output terminal under a control of a signal at a first node or a control of a signal at a second node. The node control circuit controls levels of the signal at the first node and at the second node to be opposite. The first node charging circuit includes a first control terminal, and provides a signal at a first fixed voltage terminal to the first node under a control of a signal at the first control terminal during a charging period of the first node in a non-scanning period.

A display device includes a display panel having a curved side or a polygonal side, the display panel including a plurality of pixels in a display region, a gate driver including a plurality of normal stages connected to each other for outputting gate signals to the pixels via a plurality of gate lines, and a plurality of dummy stages between some of the normal stages, and a data driver providing data signals to the pixels via a plurality of data lines.

The present disclosure provides a shift register. The shift register includes: a first node control module configured to control level at a first node based on a first clock signal and a second clock signal; a second node control module configured to control level at a second node based on level at the first node, the first clock signal, the second clock signal, a first low level signal and a high level signal; an output control module configured to control an output terminal to output high or low level based on level at the first node, level at the second node, the high level signal and a second low level signal; and a carry control module configured to control a carry terminal to output high or low level based on level at the second node, level at the output terminal, the high level signal and the second low level signal.

A shift register circuit including: a first switching unit, a second switching unit, a third switching unit, a fourth switching unit, a fifth switching unit, a sixth switching unit, a seventh switching unit, and an eighth switching unit.

There is provided in the present disclosure a shift register unit, including: a pull-up control circuit, connected to a signal input terminal and a pull-up node; a pull-up circuit, connected to the pull-up node, a first clock signal terminal and a signal output terminal; a pull-down circuit, connected to a pull-down node, the pull-up node, the signal output terminal and a power supply voltage terminal, and configured to pull down voltages of the pull-up node and the signal output terminal to a voltage of the power supply voltage terminal under the control of the pull-down node; a first pull-down control circuit, connected to a second clock signal terminal, a pull-down control signal terminal, the pull-down node and the power supply voltage terminal, and configured to pull up the voltage of the pull-down node to a valid pull-down level under the control of the pull-down control signal terminal.