A nonvolatile memory device includes a memory cell array including a plurality of nonvolatile memory cells; a page buffer circuit connected to the memory cell array through a plurality of bit lines; a calculation circuit configured to perform a calculation on information bits and weight bits based on a calculation window having a first size, the information bits and weight bits being included in a user data set, the memory cell array being configured to store the user data set, the calculation circuit being further configured to receive the user data set through the page buffer circuit; and a data input/output (I/O) circuit connected to the calculation circuit, wherein the calculation circuit is further configured to provide an output data set to the data I/O circuit in response to the calculation circuit completing the calculation with respect to all of the information bits and the weight bits, and wherein the output data set corresponds to a result of the completed calculation.

The present application discloses a display apparatus having a display area and a peripheral area. The display apparatus includes a gate-driver-on-array circuit in the peripheral area having N numbers of shift register units for respectively outputting a plurality of gate scanning signals to the plurality of gate lines. An n-th shift register unit of the N numbers of shift register units includes an input port for receiving an input signal from an output port of a m-th shift register unit through an input signal line, and a reset port for receiving a reset signal from an output port of a p-th shift register unit through a reset signal line, 1m<n<pN. At least one of the input signal line and the reset signal line includes a first segment in a same layer as a plurality of gate lines, and a second segment in a same layer as a plurality of data lines.

An object is to provide a semiconductor device which can suppress characteristic deterioration in each transistor without destabilizing operation. In a non-selection period, a transistor is turned on at regular intervals, so that a power supply potential is supplied to an output terminal of a shift register circuit. A power supply potential is supplied to the output terminal of the shift register circuit through the transistor. Since the transistor is not always on in a non-selection period, a shift of the threshold voltage of the transistor is suppressed. In addition, a power supply potential is supplied to the output terminal of the shift register circuit through the transistor at regular intervals. Therefore, the shift register circuit can suppress noise which is generated in the output terminal.

Embodiments of the present application provide a shift register unit, a method for driving the same, a gate driving circuit, and a display apparatus. The shift register unit comprises at least two sub-circuits of a first output sub-circuit, a second output sub-circuit, and a third output sub-circuit. The first output sub-circuit is configured to output a voltage at a signal output terminal to a reset signal output terminal; the second output sub-circuit is configured to output the voltage at the signal output terminal to a gating signal output terminal; and the third output sub-circuit is configured to output a voltage at a second voltage terminal to a light-emitting control signal output terminal or is configured to output a voltage at a first voltage terminal to the light-emitting control signal output terminal.

A shift register includes a gate driving signal generating sub-circuit, a plurality of first signal output control sub-circuits, second signal output control sub-circuits, and signal output terminals. Each first signal output control sub-circuit and the corresponding one of the second signal output control sub-circuits coupled thereto are configured to: during one or more time periods in a period of displaying one frame of image, transmit a gate driving signal output by the gate driving signal generating sub-circuit to a corresponding one of the signal output terminals and output the gate driving signal through the corresponding one of the signal output terminals, and during other time periods, transmit the first input signal received by the first signal input terminal to a corresponding one of the signal output terminals and output the first input signal through the corresponding one of the signal output terminals.

The embodiments of the present application provide a shift register and a method for driving the same. The shift register comprises: an input unit, a pull-up unit, a reset unit, a pull-down control unit, a pull-down unit and a pull-up holding unit. The input unit is configured to couple a first voltage terminal to a pull-up point. The pull-up unit is configured to couple a clock signal terminal to an output signal terminal. The reset unit is configured to couple a second voltage terminal to the pull-up point. The pull-down control unit is configured to selectively couple one of the second voltage terminal and a third voltage terminal to a pull-down point. The pull-down unit is configured to couple the second voltage terminal to the pull-up point and the output signal terminal. The pull-up holding unit is configured to couple a fourth voltage terminal to the pull-up point.

The present disclosure provides a shift register unit comprising a first signal input terminal, a second signal input terminal, an input and reset module, a pull-up module, a pull-down module, a pull-down control module, a clock signal input terminal, a first level input terminal, a second level input terminal, a first voltage terminal, a second voltage terminal, a signal output terminal, a discharge module and a current leakage suppression module. The present disclosure further provides a gate driving circuit, a touch display device, and a method for driving a shift register unit. A phenomenon of dark lines does not occur during display on the touch display device.

A scan line to which a selection signal or a non-selection signal is input from its end, and a transistor in which a clock signal is input to a gate, the non-selection signal is input to a source, and a drain is connected to the scan line are provided. A signal input to the end of the scan line is switched from the selection signal to the non-selection signal at the same or substantially the same time as the transistor is turned on. The non-selection signal is input not only from one end but also from both ends of the scan line. This makes it possible to inhibit the potentials of portions in the scan line from being changed at different times.

An electronic device includes clock generation circuitry. The clock generation circuitry includes a first flip flop receiving as input a device clock and being triggered by an input clock and a second flip flop receiving, as input, output from the first flip flop and being triggered by the input clock. A first inverter receives output from the first flip flop as input and a second inverter receives output from the second flip flop as input. A first AND gate receives, as input, output from the second flip flop and the first inverter, and generates a first clock as output. A second AND gate receives, as input, output from the first flip flop and the second inverter, and generates a second clock as output.

A display device with a variant-shape display region other than the rectangular display region is configured to form a scanning line drive circuit along the variant-shape display region. The scanning line drive circuit includes bus wiring group with clock wiring for supplying clocks with three or more phases and the power supply wiring for supplying power, and the unit circuits for configuring the shift register including five or more transistors. The bus wiring and the unit circuits are formed on the different regions so as not to cross with one another.