A gate driving circuit including a plurality of stages to respectively output gate signals to gate lines and connected to each other in cascade, an ith stage from among the plurality of stages including: a first output unit to generate a gate signal from a clock signal received at an input terminal; a first control unit to control the potential of a first node; a first pull-down unit to provide a first low voltage to a gate output terminal to drop down the gate signal, the first low voltage being lower than a gate off voltage of the gate signal; a first holding unit and a stabilization unit, each to provide a second low voltage having a higher level than that of the first low voltage to the gate output terminal; and a second control unit to control an operation of the first holding unit.

A first flipflop outputs a first signal synchronized with a first clock signal, a second flipflop outputs a second signal synchronized with a second clock signal, and a third flipflop outputs a third signal synchronized with a third clock signal. The second flipflop includes first to third transistors. In the first transistor, the second clock signal is input to a first terminal and the second signal is output from a second terminal. In the second transistor, a first signal is input to a first terminal, a second terminal is electrically connected to a gate of the first transistor, and the first clock signal is input to a gate. In the third transistor, the third signal is input to a first terminal, a second terminal is electrically connected to the gate of the first transistor, and the third clock signal is input to a gate.

A shift register unit, a method for driving the same, a gate driving circuit, and a display device are provided. The shift register unit includes a driving circuit, a storage capacitor circuit, an output circuit, and a reset circuit. Under the control of the start end, the driving circuit controls whether the pull-up node is connected to the set signal input end and control whether the pull-down node is connected to the first level input end. Under the control of the reset end, the reset circuit controls whether the pull-up node is connected to the first level input end, and controls whether the pull-down node is connected to the second level input end.

Provided are a drive circuit and a display apparatus capable of suppressing the delay of a drive signal. Each of multiple shift registers comprises: an output switching element to which a predetermined clock signal to be input, the output switching element comprising a second controlled terminal is connected to an output node from which a drive signal is output; a first input switching element comprising a first controlled terminal to which a set signal to be input and a second controlled terminal connected to the output switching element; and a control unit for applying a predetermined electric potential to the second controlled terminal of the output switching element-, wherein a low-level electric potential of the predetermined clock signal is lower than a low-level electric potential of the drive signal, and the predetermined electric potential is applied to the output switching element when the predetermined clock signal falls.

Embodiments of the application provide a shift register comprising a shift signal generating circuit and at least two time-sharing controlling circuits. The shift signal generating circuit may be configured to generate a shift signal. Each of the time-sharing controlling circuits comprises a first driving sub-circuit and a second driving sub-circuit, wherein the first driving sub-circuit is configured to enable the time-sharing controlling circuit to output the shift signal during the preset period, and the second driving sub-circuit is configured to enable the time-sharing controlling circuit to output an invalid signal during the non-preset period. During a driving cycle, the first driving sub-circuits in each of the at least two time-sharing controlling circuits are turned on sequentially, so that each of the at least two time-dividing controlling circuits outputs the shift signal sequentially.

A display panel and a display device including the same are discussed. The display panel includes a display area in which a plurality of data lines, a plurality of gate lines, and a plurality of sub-pixels are disposed, and a gate driver configured to supply gate signals to the gate lines. The display area includes a high-speed driving area, and a low-speed driving area driven at a frequency lower than that of the high-speed driving area. One cycle of a clock signal input to the gate driver includes a high interval with a gate high voltage and a low interval with a gate low voltage. A high interval of the clock signal is longer than a high interval of the high-speed driving area at a scanning time point of a first pixel line from which scanning of the low-speed driving area is started.

Embodiments of the present disclosure provide a display panel and a display device. The display panel includes: a base substrate including a non-display area; a gate drive circuit located in the non-display area, where the gate drive circuit includes a plurality of shift registers, and the plurality of shift registers are divided into a plurality of register sets; and a plurality of signal lead-in lines located in the non-display area, where the plurality of signal lead-in lines are divided into a plurality of line sets, a frame start signal end of one register set is correspondingly and electrically connected to one line set, and two signal lead-in lines of one line set are provided with the signal lead-in line of another line set therebetween.

A display panel and a display drive method thereof, and a display device are provided. The display panel comprises two parallel and non-overlapping display regions connected to individual scan drive circuits. The display drive method adjusts the pulse width of the light-emitting control signal for each display regions to adjust their respective light-emitting durations within a display period. This method enhances the display quality by avoiding the appearance of a yin-yang screen and improving the display brightness of each display region.

An array substrate having a display area and a peripheral area surrounding the display area, the display area is provided with display units therein, the display area includes a curved edge, the peripheral area is provided therein with a plurality of shift register units cascaded, at positions corresponding to the curved edge of the display area, an extending direction in which a first edge of each shift register unit extends is parallel to an outer tangent line of the curved edge or is consistent with an extending direction in which the curved edge extends, and the first edge is an inner edge of each shift register unit close to the curved edge.

A shift register, a display panel, and a display drive method are provided in the present disclosure. The shift register includes an input module, configured to output a first control signal according to an input signal; a pull-down control module, configured to control a potential of a first node according to a first clock signal, a high-level signal, a low-level signal, and the first control signal; a pull-up control module, configured to control a potential of a second node according to the first clock signal, a second clock signal, the high-level signal, and the first control signal; a maintaining module, configured to pull down the potential of the first node; a pull-down output module, configured to control an output terminal of the shift register to output the low-level signal; and a pull-up output module, configured to control the output terminal of the shift register to output the high-level signal.