An object is to provide a semiconductor device which can suppress characteristic deterioration in each transistor without destabilizing operation. In a non-selection period, a transistor is turned on at regular intervals, so that a power supply potential is supplied to an output terminal of a shift register circuit. A power supply potential is supplied to the output terminal of the shift register circuit through the transistor. Since the transistor is not always on in a non-selection period, a shift of the threshold voltage of the transistor is suppressed. In addition, a power supply potential is supplied to the output terminal of the shift register circuit through the transistor at regular intervals. Therefore, the shift register circuit can suppress noise which is generated in the output terminal.

A gate drive circuit and a display device are provided, wherein the gate drive circuit includes cascaded shift registers. In each shift register, a scan output terminal is electrically connected to a scan signal line, and a pull-down module transmits a voltage of a power node to the scan output terminal when the pull-down module is conducting. In odd-numbered rows, the power node electrically connects a first detection signal line, while in even-numbered rows, the power node electrically connects a second detection signal line. When the gate drive circuit is in a driving state, the first detection signal line and the second detection signal line transmit a first voltage to the scan signal lines when the pull-down modules are conducting.

A display substrate includes at least one scan driving circuit. The scan driving circuit includes a first voltage signal line, a second voltage signal line, a third voltage signal line, and shift registers. A shift register includes: first and second transistors disposed between the first voltage signal line and the second voltage signal line, third and fourth transistors disposed between the second voltage signal line and the third voltage signal line, at least one first scan signal line electrically connected to a first output terminal, and at least one second scan signal line electrically connected to a second output terminal. A second electrode of the first transistor and a second electrode of the second transistor are both electrically connected to the first output terminal; a second electrode of the third transistor and a second electrode of the fourth transistor are both electrically connected to a second output terminal.

A semiconductor device which shifts a low-level signal is provided. In an example, a first transistor including a first terminal electrically connected to a first wiring and a second terminal electrically connected to a second wiring, a second transistor including a first terminal electrically connected to a third wiring and a second terminal electrically connected to the second wiring, a third transistor including a first terminal electrically connected to a fourth wiring and a second terminal electrically connected to a gate of the second transistor, a fourth transistor including a first terminal electrically connected to a fifth wiring, a second terminal electrically connected to a gate of the third transistor, and a gate electrically connected to a sixth wiring, and a first switch including a first terminal electrically connected to the third wiring and a second terminal electrically connected to a gate of the first transistor are included.

A highly reliable semiconductor device is provided. A semiconductor device includes a shift register including a pulse output circuit formed using transistors having the same conductivity type, or the like. A transistor including a back gate is used as a transistor in which a potential difference between a source and a drain is not generated and positive stress is applied to a gate in a non-selection period of the pulse output circuit. In the non-selection period, stress applied to the transistors is reduced by interchanging the potentials of the gates and those of the back gates.

A gate driving circuit includes a plurality of driving stages applying gate signals to a plurality of gate lines of a display panel and a plurality of ripple discharge circuits discharging a ripple voltage of the gate lines. A k-th driving stage (where k is a natural number greater than 1), among the driving stages, outputs a k-th gate signal to a k-th gate line, among the gate lines, in synchronization with a first clock signal, and a k-th ripple discharge circuit, among the ripple discharge circuits, corresponding to the k-th driving stage discharges the ripple voltage of the k-th gate line to a first voltage in synchronization with a second clock signal complementary to the first clock signal.

Each unit circuit that constitutes each of stages of a shift register is provided with a charge supply unit including a third node whose potential becomes high level at identical timing with a first node (a node for holding an electric charge in order to output a scanning signal (output signal) at high level), and capable of supplying an electric charge to the first node throughout a period after the potential of the third node becomes high level until the scanning signal (output signal) at high level is outputted. Here, all of the unit circuits within the shift register have an identical configuration.

A gate driver and a touch display apparatus thereof are provided. The gate driver includes a plurality of shift registers and at least one loop circuit. The shift registers provide multiple gate signals to a touch display module. The loop circuit is coupled in series with the shift registers and receives at least one touch switching signal to set a loop time of the loop circuit. The touch display module performs at least one touch scan during the loop time.

The present application provides a reset circuit for a shift register circuit, a shift register circuit, a gate driving circuit, a display apparatus, and a driving method. The reset circuit comprises a first adjustment control circuit having an input terminal configured to receive a ground line signal, and a control terminal configured to receive a first control signal; a second adjustment control circuit having an input terminal configured to receive an adjustment signal via an adjustment signal input terminal, a control terminal configured to receive a second control signal, and an output terminal configured to be coupled to an output terminal of the first adjustment control circuit; and a storage circuit having a first terminal connected to the output terminals of the second adjustment control circuit and the first adjustment control circuit, and a second terminal connected between a reset signal input terminal and a transistor.

A transistor includes gate electrodes and light blocking films. The light blocking films are provided in a layer lower than a layer in which the gate electrodes are provided, overlap the respective gate electrodes as viewed in a plan view, shield a channel portion from light, and are electrically isolated.