The present embodiment of the invention provides a gate driving circuit and a display apparatus using the gate driving circuit. The gate driving circuit has a plurality of shift registers, and each shift register includes a first output unit, a first pull-down unit, a second output unit, a second pull-down unit, a voltage coupling unit, and a voltage boosting unit. The first output unit is coupled to a node and a first output end. The second output unit is coupled to the node and a second output end. The first pull-down unit is coupled to the first output end and a reference potential. The second pull-down unit is coupled to the second output end and the reference potential. The voltage coupling unit is coupled between the node and the second output end. The voltage boosting unit is coupled to a preset potential, the first output end, and a node and a gate high potential of a shift register at a previous stage.

An LCD device can include a liquid crystal display panel having a plurality of gate lines; a controller configured to generate at least four clock signals with different phases; a first gate driver configured to apply a high gate voltage to odd-numbered gate lines in response to at least two of the clock signals; a second gate driver configured to apply the high gate voltage to even-numbered gate lines in response to other clock signals; primary discharge circuits each configured to apply a low gate voltage to the respective odd-numbered gate line in response to a carry signal opposite to a voltage level on one of posterior odd-and-even-numbered gate lines; and secondary discharge circuits each configured to apply the low gate voltage to the respective even-numbered gate line in response to the carry signal opposite to the voltage level on the other one of the posterior odd-and-even-numbered gate lines.

A shift register is disclosed. The shift register comprises a multistage shift register units. Each of the stage shift register unit comprises: a driving module, charging to the driving signal via the first clock signal based on the driving control signal; an input module, outputting the driving control signal based on the second clock signal and the first control signal; a low level maintenance module, keeping the potential of the driving signal at the low level potential of the second reference. The shift register can avoid the leakage from the first output end, decrease the raising time of the driving signal and occupy the small area.

The disclosure provides a scan driving circuit and a flat display device, the scan driving circuit includes a plurality of cascaded scan driving units, each of the scan driving units includes a forward/backward scanning circuit, applied to receive and process a superior level transmitted signal and a first inferior level transmitted signal, so as to control the scan driving circuit to scan forward and backward; an input circuit charges a pull-up control signal point and a pull-down control signal point according to the superior level transmitted signal and the first inferior level transmitted signal; a latch circuit latches the superior level transmitted signal and the first inferior level transmitted signal; a reset circuit clears and resets electric potential of the pull-up control signal point; a signal multiplexing circuit processes a same level transmitted signal, a second inferior level transmitted signal and latch data.

A shift register unit, a driving method thereof, a gate driver circuit and a display device are provided. The shift register unit includes a first pull-up node control unit, a second pull-up node control unit configured to enable a pull-up node to be at a first level at a pull-down maintenance stage under the control of a first clock signal, a first pull-down node control unit configured to enable a pull-down node to be at a second level at the pull-down maintenance stage under the control of the first clock signal, a second pull-down node control unit, a gate driving signal output unit configured to output a gate driving signal under the control of the pull-up and pull-down nodes, and a carry signal output unit configured to enable a carry signal output end to output a carry signal under the control of the pull-up and pull-down nodes.

The present disclosure relates to an array substrate, a display panel and a display device. The array substrate includes a plurality of shift register units, a plurality of gate lines and a plurality of data lines crossing the plurality of gate lines. The plurality of gate lines crossing the plurality of data lines defines a plurality of pixel regions. Each of the pixel regions is divided into a driving zone and a pixel unit zone. A plurality of the driving zones in a same column constitute at least one unit region and each of the shift register units is disposed in one of the unit regions to provide scanning signals to the gate line connected thereto.

The present disclosure provides a shift register circuit, an array substrate, and a display device. For a first driver and a second driver adjacent to each other in a direction substantially perpendicular to the gate line, a first driving input wiring of the first driver is arranged to input a first clock driving signal to individual shift registers successively from a shift register at a first end position of the first driver to a shift register at a second end position of the first driver, and a second driving input wiring of the second driver is arranged to input a second clock driving signal to individual shift registers successively from a shift register at a second end position of the second driver to a shift register at a first end position of the second driver.

A shift register and a display apparatus are provided. The shift register includes a pre-charge unit, a pull-up unit, a first pull-down unit and a second pull-down unit. The pre-charge unit receives first and second input signals, and outputs a pre-charge signal via a first node. The pull-up unit receives a pre-charge signal and a clock signal, and outputs a scanning signal via a second node. The first pull-down unit receives the pre-charge signal, first and second pull-down control signals, and controls whether to pull-down the scanning signal to a reference voltage level. The second pull-down unit receives the pre-charge signal, first and second pull-down control signals, and controls whether to keep the scanning signal at the reference voltage level. The duty cycle of the clock signal is less than 50 percent.

A shift register unit comprises an input subcircuit for a first node to be a first level when a scan pulse is of the first level, an output subcircuit for driving an output terminal to be a first clock signal level when the first node is at the first level, a second node control subcircuit for connecting the second node with a second level when either of the scan pulse and the output terminal is of the first level, and connecting the second node with the first level when each of the scan pulse and the output signal is of the second level, a first reset subcircuit for driving the first node to be the second level when the second node is at the first level, and a second reset subcircuit for driving the output signal to be the second level when the second node is at the first level.

An electronic display includes an active area including multiple pixels. The electronic display also includes a first row driver set including a first column of row drivers and a second column of row drivers. A first active row driver in the first column of row drivers drives a first portion of the multiple pixels, and a first spare row driver in the second column of row drivers is in an inactive state. The electronic display also includes a second row driver set including a third column of row drivers and a fourth column of row drivers. A third active row driver in the third column of row drivers drives a second portion of the multiple pixels, and a second spare row driver in the fourth column of row drivers is inactive.