The embodiments of the present disclosure disclose a shift register, a method for driving the same, and a gate driving circuit. The shift register may include an inputting circuit, configured to apply a signal at a first signal terminal to a pulling up node; a resetting circuit, configured to apply a signal at a second signal terminal to the pulling up node; an outputting circuit, configured to apply a signal at a first clock terminal to an outputting terminal; a pulling down circuit, configured to apply a signal at a constant level terminal to the pulling up node and the outputting terminal according to the potential at a pulling down node, and to apply a signal at the constant level terminal to the pulling up node and the outputting terminal; a pull-down controlling circuit, configured to control the potential at the pulling down node; and a storage capacitor.

A shift register includes a first scan unit including a first input circuit and a first output circuit, and a second scan unit including a second input circuit, a second output circuit, and a potential boost circuit. The first input circuit is configured to transmit an input signal to a first pull-up node. The first output circuit is configured to, under a control of a voltage of the first pull-up node, output a shift signal and a first scan signal. The second input circuit is configured to transmit the input signal to a second pull-up node. The second output circuit is configured to output a second scan signal under a control of a voltage of the second pull-up node. The potential boost circuit is configured to boost the voltage of the second pull-up node in cooperation with the second output circuit.

An apparatus that includes a shift register unit, a gate driving circuit, and a display apparatus. The shift register unit includes: an input circuit, a reset circuit, a node control circuit, a cascade output circuit and a drive output circuit, where the drive output circuit is configured to provide the signal of the clock signal end to a drive output end in response to the signals of the first node.

A shift register unit, a gate drive circuit, a display apparatus and a driving method. The shift register unit includes: a first control circuit, configured to control a signal of a first node and a signal of a second node according to a signal of an input signal end and a signal of a first clock signal end; second control circuits, configured to control signals of at least two drive nodes according to the signal of the first node, the signal of the second node and signals of second clock signal ends; cascade output circuits, configured to provide the signal of one of the at least two drive nodes to a cascade output end according to cascade selection signal ends; and drive output circuits, configured to provide the signal of at least one of the at least two drive nodes to drive output ends corresponding to the drive nodes.

A shift register, a driver circuit, a display panel, and a display apparatus. In the shift register, a first input unit is configured to write a signal into a first node; a first output unit includes a control terminal coupled to the first node, a first terminal receiving a first voltage signal, and a second terminal coupled to a signal output terminal; a second input unit is configured to write a signal into a second node; a second output unit includes a control terminal coupled to the second node, a first terminal receiving a first clock signal, and a second terminal coupled to the signal output terminal; a holding unit includes an output terminal coupled to the second node, and is configured to maintain a potential of the second node at least during a period when the first output unit is off and the second output unit is on.

A transistor whose channel region includes an oxide semiconductor is used as a pull down transistor. The band gap of the oxide semiconductor is 2.0 eV or more, preferably 2.5 eV or more, more preferably 3.0 eV or more. Thus, hot carrier degradation in the transistor can be suppressed. Accordingly, the circuit size of the semiconductor device including the pull down transistor can be made small. Further, a gate of a pull up transistor is made to be in a floating state by switching of on/off of the transistor whose channel region includes an oxide semiconductor. Note that when the oxide semiconductor is highly purified, the off-state current of the transistor can be 1 aA/?m (1?10.sup.?18 A/?m) or less. Therefore, the drive capability of the semiconductor device can be improved.

A display panel and a display device. The display panel comprises: a substrate, a display area (100) provided with at least one light-emitting signal line (E), at least one first reset signal line (R) and sub-pixels arranged in an array, at least one sub-pixel (P1, P2, P3) comprising: a light-emitting device (L) and a pixel circuit. The first reset signal line (R) is configured to provide a reset control signal for the pixel circuit, the light-emitting signal line is configured to provide a light-emitting control signal for the pixel circuit to provide a driving current. For the first reset signal line and the light-emitting signal line connected to a same pixel circuit, the duration in which the signal of the light-emitting signal line is an invalid level signal is equal to the duration in which the signal of the first reset signal line is a valid level signal.

A pixel driving circuit, a display panel and a driving method therefor, and a display device, related to the display field and aiming to enable the pixel driving circuit to work in different operating modes to adapt to various application scenarios. The pixel driving circuit includes a driving transistor, a gate writing module and a control module. The control module and the gate writing module are connected in series on a function signal transmission path between a function signal terminal and a gate electrode of the driving transistor, and the gate writing module is configured to provide a function signal at the function signal terminal to the gate electrode of the driving transistor. An operating process of the pixel driving circuit includes a stage in which the gate writing module is turned on and the control module is turned off.

A shift register unit includes: an input circuit configured to provide an input signal to a first node in response to a first clock signal; a reset circuit configured to provide a first reference signal to a second node in response to a second clock signal; a first control circuit configured to provide the second clock signal to the second node in response to a first control signal; an output circuit configured to provide a third clock signal to a drive output terminal in response to a signal of the first node, and provide a second reference signal to the drive output terminal in response to a signal of the second node; where a duration of an active level of the first control signal is longer than a duration of an active level of a signal of the drive output terminal.

The present application provides a gate drive circuit, a drive device and a display device. The gate drive circuit includes m switch groups, n first shift registers and m second shift registers. Each switch group includes n first switch units. The n first shift registers cyclically output a first row-scan signal, while each second shift register controls the n first switch units connected to each first controlled node corresponding to the second shift register to be turned on, so that the first row-scan signal is fed back to each gate-line in turn, to realize a line-by-line scan driver. The gate drive circuit only needs n+m shift registers to complete the gate drive, compared with the existing gate drive circuit requiring n?m shift registers, the number of shift registers is reduced, the cost is reduced and the manufacturing process is simplified.