An array substrate and a method for forming the same are provided. The array substrate includes: a gate driver in a non-display area, wherein the gate driver includes M shift register circuits and each shift register circuit includes two shift register groups, which includes N shift registers each, where M is a positive even number and N is a positive integer greater than 2; in each of the shift register groups, a gate output end of an n.sup.th shift register has signal wires; along a direction perpendicular to the non-display area, at least one of the signal wires of one shift register group are stacked above at least one of the signal wires of another shift register group. Accordingly, a display panel using this array substrate may realize a narrow side frame design.

Provided are an organic light-emitting display panel and an organic display device, the organic light-emitting display panel includes: a display region and at least one peripheral circuit region; the peripheral circuit region is provided with shift registers cascaded in stages and clock signal lines of at least two different types, the number of clock signal lines in at least one of the different types is not less than 2, clock signals of one type of the clock signal lines are the same, clock signals of different types of the clock signal lines are different; the clock signal lines each is electrically connected to a clock signal input terminal of one of the shift registers, the shift registers each is configured to output a gate driving signal according to the clock signal in the clock signal line electrically connected to the input terminal of one of the shift registers.

To provide an electronic circuit and the like capable of extending the life greatly even when the transistors constituting the electronic circuit have property fluctuation. The electronic circuit includes switching-target circuits and a switching circuit for switching the switching-target circuits to an operating state from a stop state. The switching-target circuits include the switching-target circuit in an operating state and the switching-target circuit in an initial-to-stop state. Property fluctuation is generated in the transistors forming the switching-target circuits and the switching target due to an electric stress applied to the transistors. The switching circuit switches the switching-target circuit in the initial-to-stop state to an operating state by the transistor of the switching circuit.

The present invention provides a scan driver and a display using the same. The scan driver includes multiple stages of driving units. The driving units are controlled by a start signal, a clock signal and at least one selection signal. The i.sup.th stage of the driving unit includes a shift register and a de-multiplexer. The shift register generates a scan signal according to the clock signal and a trigger signal. The de-multiplexer selectively outputs the scan signal to multiple scan lines according to the at least one selection signal. The trigger signal of the 1.sup.st stage of the driving unit is the start signal, and the trigger signal of the (i+1).sup.th stage of the driving unit is the scan signal of the i.sup.th stage of the driving unit.

There are provided a shift register unit, a strobe driving circuit, a display apparatus and a driving method for the shift register unit. The shift register unit comprises: an inputting module (10) configured to control a potential of the pulling-up control node according to a signal of the first signal input terminal; a pulling-up module (20) configured to output a present stage output signal from the present stage output terminal according to a signal of the second clock signal terminal and the potential of the pulling-up control node; a pulling-down module (30) configured to pull down the potential of the pulling-up control node and the signal of the present stage output terminal to a low level according to a signal of the third clock signal terminal; a resetting module (40) configured to reset the potential of the pulling-up control node according to a signal of the second signal input terminal and pull down the signal of the present stage output terminal to a low level. Correspondingly, the pulling-down operation of the shift register unit is implemented in a simple manner, so that a number of TFTs as required, power consumption and wiring are reduced.

The invention provides a gate driving circuit and a display device. The gate driving circuit is configured to drive a display panel of the display device, and includes shift registers and at least a dummy shift register. The shift registers are respectively configured to generate and output scan signals to scan lines of the display panel, the dummy shift register is configured to generate a dummy scan signal before the scan signals are generated. The dummy scan signal and the scan signals are sequentially generated.

A gate drive integrated circuit (IC) for a display device includes a start pulse modulator configured to receive a start pulse or a front-end carry pulse alternating between a first logic level and a second logic level to output a modulation start pulse or a modulation carry pulse that is generated by modulating a logic level shift time of the start pulse or the front-end carry pulse; and a shift register configured to receive and sequentially output the modulation start pulse or the modulation carry pulse. The start pulse modulator is further configured to output the modulation start pulse or the modulation carry pulse having the second logic level at a time when a logic level of the start pulse or the front-end carry pulse has a third logic level between the first logic level and the second logic level.

A supplement resetting module for a gate driver circuit, including a pull-up control unit, a pull-down control unit, a clock signal input end, a predetermined level input end, a first control signal input end, a second control signal input end and a signal output end. A control end of the pull-up control unit is connected to the clock signal input end, an output end of the pull-up control unit is connected to the signal output end, a first control end of the pull-down control unit is connected to the first control signal input end, a second control end of the pull-down control unit is connected to the second control signal input end, an input end of the pull-down control unit is connected to the predetermined level input end, and an output end of the pull-down control unit is connected to the signal output end.

A drive circuit, a display panel, a display device and a drive method. The drive circuit includes a plurality of shift registers; a first switch circuit connected with the shift registers, which is configured to selectively output output signals the shift registers or a first voltage based on a first control signal and a second control signal; and a second switch circuit connected with the shift registers, which is configured to selectively output the output signals of the shift registers or the first voltage based on a third control signal and a fourth control signal. A set of shift registers can simultaneously or individually drive two display regions.

A shift register for a display device. The shift register may include a shift register processing circuit (10) and a control circuit (20). A first terminal of the control circuit (20) may be coupled to an output terminal (Qn) of the shift register processing circuit (10), a second terminal of the control circuit (20) may be coupled to an output terminal of the shift register (Output), and a third terminal of the control circuit (20) may be coupled to a control signal terminal (T0). The shift register may be configured to output a final gate line scan signal from the output terminal of the shift register (Output), and a starting point of the final gate line scan signal is later than a starting point of a gate line scan signal outputted from the output terminal (Qn) of the shift register processing circuit (10).