Disclosed are a shift register unit, an operation method therefor and a shift register including the shift register unit. The shift register unit includes: an input module configured to transmit a received input signal to a pull-up node; an output module configured to output a first control signal of a first control signal end to an output end when a pull-up signal at the pull-up node is at an effective pull-up level; and a coupling module having a first end connected to a second control signal end and a second end connected to the pull-up node, and being configured to control the pull-up signal at the pull-up node in a voltage coupling manner according to a second control signal of the second control signal end. By further pulling up the voltage at the pull-up node when output end is reset, the speed of resetting the output end can be increased.

A shift register unit comprises an input subcircuit for driving a first node to be a first level when a scan pulse is of the first level, an output subcircuit for driving an output terminal to be a first clock signal level when the first node is at the first level, a second node control subcircuit for connecting the second node with a second level when either of the scan pulse and the output terminal is of the first level, and connecting the second node with the first level when each of the scan pulse and the output signal is of the second level, a first reset subcircuit for driving the first node to be the second level when the second node is at the first level, and a second reset subcircuit for driving the output signal to be the second level when the second node is at the first level.

Disclosed herein is an electronic device including a flip flop and clock generation circuitry for controlling the flip flop. The flip flop includes a master latch receiving input for the flip flop, with the master latch latching the received input to its output in response to a first clock. The slave latch receives input from the output of the master latch, and latches the received input to its output in response to a second clock. The clock generation circuitry is configured to logically combine a device clock and an input clock to produce the first and second clocks.

A shift register unit and a control method thereof, a gate drive device including the shift register unit, and a display device. The shift register unit includes: an input module, a pull-up module, a first pull-down control signal generation module, controlling, in the period that a first signal is high level, potential of a first pull-down control node according to a drive input signal and potential of a pull-up control node; a second pull-down control signal generation module, controlling, in the period that a second signal is high level, potential of a second pull-down control node according to the drive input signal and the potential of the pull-up control node, the first signal and the second signal alternatively becoming high level; and a pull-down module, pulling down a drive output signal according to the potential of the first pull-down control node and the potential of the second pull-down control node.

The present invention provides a shift register and a driving method thereof, a driving circuit, and a display device, the shift register includes an input unit, an output unit and a reset unit, the input unit controls potential of a first node according to input signals of an input terminal and a first voltage terminal, the output unit controls an output signal of an output terminal according to input signals of the input terminal and a clock signal terminal under the control of the potential of the first node, and the reset unit controls potential of a second node according to input signals of a reset terminal and a second voltage terminal.

The scanning line drive circuit has a configuration in which a plurality of unit circuits are connected in multiple stages. A unit circuit includes: a first transistor having a first conductive terminal to which a first-level voltage is applied and a second conductive terminal connected to a first node; a second transistor having a second conductive terminal to which a second-level voltage is applied; a third transistor having a first conductive terminal connected to the first node and a second conductive terminal connected to a first conductive terminal of the second transistor; a fourth transistor having a first conductive terminal connected to a control terminal of the third transistor, and having a second conductive terminal and a control terminal to both of which the second-level voltage is applied; and an output transistor having a control terminal connected to the first node and a second conductive terminal connected to an output terminal.

A display substrate and a display apparatus are provided, wherein the display substrate includes a display area and a non-display area, wherein the non-display area includes a first bezel area and a transition area, the transition area including a first transition area; the display substrate includes a light emitting drive circuit, a scanning drive circuit, and a control drive circuit; the light emitting drive circuit includes multistage light emitting shift registers, the scanning drive circuit includes multistage scanning shift registers, and the control drive circuit includes multistage control shift registers; the first bezel area includes a first circuit group, the first transition area includes a second circuit group, and the first circuit group and the second circuit group include a Q1-stage light emitting shift register, a Q2-stage scanning shift register, and a Q3-stage control shift register.

A shift register, a gate driving circuit, and a display device are provided. The shift register includes an input unit, a first control unit, a second control unit, a voltage gating unit, an output unit, an energy storage unit and a reset unit. The shift register can output dual driving signals with fewer switching elements. When it is applied to the gate driving circuit, the total number of switching elements included in the gate driving circuit can be reduced, the wiring can be simplified, and the area occupied by the gate driving circuit can be decreased, thereby facilitating narrowing to the frame of the display device.

A shift register circuit and a driving method therefor, a gate line driving circuit and an array substrate, the shift register circuit includes: a charging sub-circuit for charging a pull-up node under the control of a signal input by an input signal terminal; an output sub-circuit for outputting, through an output terminal, a clock signal provided by a first clock signal terminal to serve as a drive signal, under control of an electric level of the pull-up node; a first pull-down sub-circuit for pulling down the pull-up node and the output terminal under the control of an electric level of a first pull-down node; and a reset sub-circuit for resetting the pull-up node and the output terminal under the control of a reset signal input by a reset signal terminal.

The CMOS GOA circuit of reducing clock signal loading comprises the input control module (1), the latch module (2), the reset module (3), the signal process module (4) and the output buffer module (5); in the input control module (1), the clock signal (CK(M)) merely needs to control the second N type thin film transistor and the fifth N type thin film transistor (T2, T5), and the amount of the thin film transistors driven by the clock signal can be decreased to reduce the clock signal loading, and to lower the RC delay and the power consumption of the clock signal; the latch module (2) utilizes the inverted scan drive signal (XGate(N2)) of the two former N-2th stage GOA unit to be the input control signal of the stage transfer signal Q(N) to solve the competition problem occurs as the stage transfer signal (Q(N)) is inputted.