The present disclosure relates to the display technologies, which provides a GOA unit, a GOA circuit, a display driving circuit and a display device, for outputting a gate driving signal and a reset signal of a pixel electrode through a GOA unit, to simplify the display driving circuit. The GOA unit comprises a first node control module, a second node control module, a third node control module, a first output module and a second output module, wherein the first output module outputs the gate driving signal under the control of the node voltage of a first node, the node voltage of a second node and a second input signal inputted at a second input terminal; and the second output module outputs the reset signal of the pixel electrode under the control of the node voltage of the second node, the node voltage of the third node and a third input signal inputted at a third signal input terminal.

The embodiments of the present disclosure disclose a gate driving circuit and a display panel. In the gate driving circuit, a control unit of a shift register may input a dual pulse control signal to a first control terminal of an output unit; and the output unit outputs a scanning signal having a pulse width equal to a pulse period of the dual pulse control signal to a corresponding gate line under the control of the dual pulse control signal. In this way, the output unit is controlled by the control unit to output a scanning signal of which a pulse width may be modulated, so as to output a gate signal of which a pulse width may be modulated.

Disclosed is a shift register unit, a gate driving circuit and a driving method, as well as a display apparatus. The shift register unit has a working cycle including an input phase, an output phase, a reset phase and a maintaining phase. In the reset phase, a clock signal is transmitted to an output terminal to pull a voltage of the output terminal down to a reference voltage, and the pulled-down voltage of the output terminal is subsequently changed from the reference voltage to a gate-off voltage. In the maintaining phase, the voltage of the output terminal is maintained at the gate-off voltage. The reference voltage is smaller than the gate-off voltage.

A display panel includes pixel driving circuits distributed in an array and forming pixel driving circuit groups, each pixel driving circuit group includes pixel driving circuit rows with each including pixel driving circuits, each of which includes a driving circuit connected to a first, second and third nodes, to input a driving current to the third node through the second node in response to a signal of the first node; a first switching unit with a first end connected to a first power supply terminal and second end connected to the second node, to connect the first power supply terminal and the second node in response to a pulse width modulation signal; in a same pixel driving circuit group, a second end of any first switching unit is connected to a second end of at least one first switching unit in each of the other pixel driving circuit rows.

A scan circuit is provided. The scan circuit includes a plurality of stages. A respective stage of the scan circuit includes a respective scan unit configured to provide a control signal to one or more rows of subpixels. A respective scan unit includes a first subcircuit, a second subcircuit, a third subcircuit, a fourth subcircuit. A pull-up node is coupled to the second subcircuit, the third subcircuit, and the fourth subcircuit. A pull-down node is coupled to the second subcircuit, the third subcircuit. The denoising subcircuit is coupled to a pull-up node and the input terminal, or coupled between a third power supply voltage terminal and the pull-down control node.

Provided in the embodiments of the present discourse are a display panel, a driving method for the same, and a display device. The display panel includes: a first shift register including a plurality of cascaded first shift units; a first signal line electrically connected to the plurality of first shift units for providing a level voltage required to be output by the first shift units; and a second signal line receiving a same level voltage as the first signal line, where at least one switch unit is connected between the second signal line and the first signal line. The display panel has a first mode, and in the first mode, the first shift units output at least two pluses within one frame, and at least a part of the switch units are turned on.

The embodiments of the present application provide a shift register and a method for driving the same. The shift register comprises: an input unit, a pull-up unit, a reset unit, a pull-down control unit, a pull-down unit and a pull-up holding unit. The input unit is configured to couple a first voltage terminal to a pull-up point. The pull-up unit is configured to couple a clock signal terminal to an output signal terminal. The reset unit is configured to couple a second voltage terminal to the pull-up point. The pull-down control unit is configured to selectively couple one of the second voltage terminal and a third voltage terminal to a pull-down point. The pull-down unit is configured to couple the second voltage terminal to the pull-up point and the output signal terminal. The pull-up holding unit is configured to couple a fourth voltage terminal to the pull-up point.

A scan line to which a selection signal or a non-selection signal is input from its end, and a transistor in which a clock signal is input to a gate, the non-selection signal is input to a source, and a drain is connected to the scan line are provided. A signal input to the end of the scan line is switched from the selection signal to the non-selection signal at the same or substantially the same time as the transistor is turned on. The non-selection signal is input not only from one end but also from both ends of the scan line. This makes it possible to inhibit the potentials of portions in the scan line from being changed at different times.

A display panel includes a shift register and an active terminator. The shift register has a drive circuit coupled to one end of a gate line. The active terminator is coupled to the other end of the gate line and includes a first transistor, a second transistor, and a first capacitor. The first transistor has a first terminal connected to a first clock signal, a second terminal connected to the gate line, and a third terminal. The second transistor has a first terminal connected to a first internal node, a second terminal connected to the third terminal of the first transistor, and a third terminal connected to a first DC voltage source. The first capacitor has a first terminal connected to the gate line and a second terminal connected to the third terminal of the first transistor and the second terminal of second transistor.

Provided are a shift register unit and a driving method thereof, a scan driving circuit, a display device, wherein the shift register unit comprises an input module configured to output a voltage at the signal input terminal to the first node, an energy storage module configured to store the voltage at the first node or to charge the first node, a first pull-up control module configured to output a voltage at the first voltage terminal to the pull-up control node, a second pull-up control module configured to output a voltage at the second voltage terminal to the pull-up control node, a pull-down control module configured to output a voltage at the first node to the pull-down control node. The pulse width of the signal of each stage of output terminal of the GOA circuit can be adjusted.