A bidirectional shift register capable of performing a stable shift operation in both directions and an image display device using the same are provided. In forward shift operation, when reference point N1 is at H level, (n+4)-th unit register circuit as a rear stage of the bidirectional shift register outputs pulse G(n+4) in synchronization with clock pulse V(n+4) inputted to (n+4)-th unit register circuit. A backward direction trigger signal VSTB is generated not only at the time of start of backward shift, but also, for example, in period (time t4 to t5) of one-phase clock immediately after G(n+4) is outputted in vertical blanking interval of the forward shift. The backward direction trigger signal VSTB is inputted to gate of a transistor provided to set reference point N1 of (n+4)-th unit register circuit to H level at the time of start of the backward shift.

The present disclosure provides a gate driving circuit and a display apparatus, wherein the gate driving circuit comprises a shift register (10) including a plurality of shift register units connected with each other sequentially, and the gate driving circuit further comprises: a first strobe module (20) and/or a second strobe module (30); the first strobe module (20), connected to a gate scanning trigger signal line (STV) and strobe signal lines (CS0, CS1); the second strobe module (30), connected to the strobe signal lines. With incorporation of the first strobe module (20), a gate scanning trigger signal on a gate scanning trigger signal line (STV) is supplied to a predetermined shift register unit according to strobe signals provided on the strobe signal lines (CS0, CS1); and the second strobe module (30), which is configured to cut off communication between the predetermined shift register unit and its previous stage of shift register unit according to the strobe signals provided on the strobe signal lines (CS0, CS1), so that the shift register is turned off from the predetermined shift register unit, and thus it can be achieved on a liquid crystal display panel that the gate signal(s) in a black-scan area are selectively turned off in a partial display mode, thus power consumption of the whole display panel being reduced.

A gate drive circuit is disclosed. The gate drive circuit includes shift register units connected with gate lines. The gate drive circuit also includes clock signal lines to provide clock signals. A trigger signal terminal of the first shift register unit is connected with a first initial trigger signal line, and a trigger signal terminal of the p-th shift register unit is connected with an output terminal of the (p−1)-th shift register unit. An end signal terminal of the r-th shift register unit is connected with an output terminal of the (r+2.sup.M-1)-th shift register unit, low level signal terminals are connected with a first low level signal line, and reset signal terminals are connected with a reset signal line. In addition, forward scan signal terminals are connected with a first scan signal line, and backward scan signal terminals are connected with a second scan signal line.

Disclosed is a display device including a light emission driver configured to sequentially generate a plurality of light emission signals having a disable level during a first period; and a scan driver configured to generate a plurality of shift outputs each having two enable pulses, and each outputting two scan signals, in response to two light emission signals among the plurality of light emission signals, by dividing the two enable pulses of a first shift output among the plurality of shift outputs, which correspond to the two light emission signals among the plurality of light emission signals, from each other.

The present disclosure provides a gate driving circuit comprising multiple stages of cascaded shift registers, each stage of shift register comprising an input subcircuit, a first reset subcircuit, a second reset subcircuit, an energy storage subcircuit, an output subcircuit and a pull-down node potential generation subcircuit, wherein at least two stages of shift registers share a pull-down node potential generation subcircuit. The present disclosure further provides a display panel comprising the gate driving circuit, and a method for driving the gate driving circuit.

A display panel, a shift register circuit, and a driving method of the shift register circuit are provided. The shift register circuit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, a first capacitor, and a second capacitor. When turned on individually, the first transistor provides an input signal to a second node, the second transistor provides the input signal to the first node, the third transistor provides a charging signal to a second node, the fourth transistor provides a first voltage signal to a third node, the fifth transistor provides a voltage signal at the third node to the first node, the sixth transistor provides the first voltage signal to a signal output terminal, and the seventh transistor provides the second clock signal to the signal output terminal.

A shift register, a method and a system for operating the shift register are provided. The shift register includes: an input circuit adapted to output a first voltage signal in response to an input signal; a trigger circuit adapted to generate a second voltage signal based on a first reference voltage and a second reference voltage, in response to the first voltage signal; and generate a third voltage signal, different than the second voltage signal, based on the first reference voltage and the second reference voltage, in response to the first voltage signal; and an output circuit adapted to output a scanning signal based on the second voltage signal and the third voltage signal. The voltages of the second voltage signal and the third voltage signal depend on a voltage dividing value of the trigger circuit, and the voltage dividing value of the trigger circuit is based on the first reference voltage and the second reference voltage.

A shift register, a driving method, a gate driving circuit and a display device are disclosed. The input module controls the potential of the first node. The first reset module controls the potential of the first node. The second reset module controls the potential of the driving signal output terminal. The first output module controls the potential of the driving signal output terminal under the control of the first node. The second output module controls the potential of the driving signal output terminal under the control of the second node. The pull-down driving module controls the potentials of the first node and the second node. Since the node control signal at the node control signal terminal can eliminate the noise on the first node resulting from the change in the first clock signal, the output stability of the shift register can be improved.

The present disclosure provides a shift register unit. The shift register unit includes an input module, a first resetting module, an energy storage module, a first enhanced resetting module, an output control module, a first input terminal, a second input terminal, a third input terminal, a fourth input terminal, a fifth input terminal, a sixth input terminal, a shift driving signal output terminal, and a first node. A first terminal of the energy storage module is connected to the first node. The input module is connected to the first node, the first input terminal, and the second input terminal. The output control module is connected to the first node, the third input terminal, and the shift driving signal output terminal. The first resetting module is connected to the first node, the fourth input terminal, and the fifth input terminal.

Provided are a shift register unit and a driving method thereof, a scan driving circuit, a display device, wherein the shift register unit comprises an input module configured to output a voltage at the signal input terminal to the first node, an energy storage module configured to store the voltage at the first node or to charge the first node, a first pull-up control module configured to output a voltage at the first voltage terminal to the pull-up control node, a second pull-up control module configured to output a voltage at the second voltage terminal to the pull-up control node, a pull-down control module configured to output a voltage at the first node to the pull-down control node. The pulse width of the signal of each stage of output terminal of the GOA circuit can be adjusted.