A display panel includes shift registers coupled in serial. At least one of the shift registers includes an input circuit, an output circuit and a control circuit. The input circuit is coupled to a first input terminal and a second input terminal for respectively receiving a first input signal and a second input signal. The output circuit is coupled to a first clock input terminal for receiving a first clock signal and outputting a pulse signal at an output terminal according to the first clock signal. The control circuit is coupled to the output circuit via a first control node, a second control node and a third control node and controls voltages at the first control node, the second control node and the third control node according to the first input signal or the second input signal, and further controls operations of the output circuit.

The invention discloses a shift register element, a method for driving the same, and a display panel, where the shift register element includes an input module, a first control module, a second control module, a feedback and adjustment module, an output module, a first coupling module, and a second coupling module; the feedback and adjustment module feeds a signal from the output signal terminal back to a first node under the control of the second clock signal terminal, and the second control module connects the first node with a third node under the control of a first signal; and the first control module provides a second node with a signal of the first clock signal terminal or the first signal terminal under the control of a first clock signal terminal.

Provided is a gate driving circuit including driving stages which provide a plurality of pixels of a display panel with gate signals, wherein any one of the driving stages includes a thin film transistor including a first control electrode, an activation part overlapping the first control electrode, an input electrode overlapping the activation part, an output electrode overlapping the activation part, and a second electrode disposed on the first control electrode and the activation part; and a capacitor including a first electrode disposed on the layer on which the first control electrode is disposed, a second electrode, which overlaps at least a portion of the first electrode and is disposed on the layer on which the input electrode is disposed, and a third electrode which overlaps the first and second electrodes and is electrically connected to the first electrode.

The present disclosure provides a gate driver circuit including at least one set of clock signal lines and multiple levels of shift registers arranged in a cascaded manner. Each set of the clock signal lines includes two clock signal lines. The multiple levels of shift registers is divided into at least one set, and each set of the clock signal lines corresponds to a set of the shift registers. One clock signal line in each set of the clock signal lines is connected to a resetting signal input end of a last-level shift register in the set of the shift registers corresponding to the set of the clock signal lines. The present disclosure further provides an array substrate, a display device and a method for driving the gate driver circuit.

The invention discloses a GOA circuit, a display device and a drive method of a GOA circuit, the GOA circuit is set to be GOA units including a plurality of levels, a N leveled GOA unit is applied to charge a N leveled scanning line of a display region of the display device, the N leveled scanning line is connected to a first gate all on signal and a second gate all on signal, which can guarantee scanning lines corresponding to all the GOA units are being charged under control of the first gate all on signal and the second gate all on signal. The invention can carry out an all gate on function according to the method above.

The present disclosure provides a shift register circuit, an array substrate, and a display device. For a first driver and a second driver adjacent to each other in a direction substantially perpendicular to the gate line, a first driving input wiring of the first driver is arranged to input a first clock driving signal to individual shift registers successively from a shift register at a first end position of the first driver to a shift register at a second end position of the first driver, and a second driving input wiring of the second driver is arranged to input a second clock driving signal to individual shift registers successively from a shift register at a second end position of the second driver to a shift register at a first end position of the second driver.

A shift register, gate drive circuit and display panel are provided. The shift register includes a latch unit, a NAND gate unit, a buffer unit and a switch unit. The latch unit, the NAND gate unit and the buffer unit are configured to produce a scanning driving signal and a scanning stopping signal. The latch unit is configured to control the switch unit to be turned on so as to output the scanning driving signal or the scanning stopping signal from the output terminal of the shift register, or control the switch unit to be turned off so as to enable the output terminal of the shift register to float.

The embodiments of the present disclosure provide a shift register unit, a method for driving the shift register unit, a gate driving circuit and a display apparatus. The shift register unit comprises a first input module, a first output module, a first reset module, a first storage module and a second reset module. The first input module is configured to output a first pull-up signal to the first output module based on a first input signal. The first output module is configured to output an output signal based on the first pull-up signal and a first clock signal. The first storage module is configured to store the first pull-up signal. The first reset module is configured to reset the first storage module based on a first reset signal. The second reset module is configured to reset the output from the first output module based on a second reset signal. The second reset signal is set to be valid while the first pull-up signal and the first clock signal are valid and a duration in which the second reset signal is valid is shorter than a duration in which the first clock signal is valid.

Embodiments of the present disclosure provide a display panel and a display device. The display panel includes: a base substrate including a non-display area; a gate drive circuit located in the non-display area, where the gate drive circuit includes a plurality of shift registers, and the plurality of shift registers are divided into a plurality of register sets; and a plurality of signal lead-in lines located in the non-display area, where the plurality of signal lead-in lines are divided into a plurality of line sets, a frame start signal end of one register set is correspondingly and electrically connected to one line set, and two signal lead-in lines of one line set are provided with the signal lead-in line of another line set therebetween.

Embodiments of the present disclosure disclose a shift register. The shift register comprises an input circuit configured to control a voltage of a first node, an output circuit configured to control an output signal of a signal output terminal, a first reset circuit configured to reset the voltage of the first node, a second reset circuit configured to reset the output signal, a pull-up control circuit configured to control the voltage of the first node according to the voltage of the second node, and a pull-down control circuit configured to control the voltage of the second node according to the voltage of the first node and control the voltage of the second node to be an effective voltage in response to the voltage of the first node being a non-effective voltage. Further, a gate driving apparatus, an array substrate, and a display apparatus are also proposed.