A shift register is disclosed. The shift register comprises a multistage shift register units. Each of the stage shift register unit comprises: a driving module, charging to the driving signal via the first clock signal based on the driving control signal; an input module, outputting the driving control signal based on the second clock signal and the first control signal; a low level maintenance module, keeping the potential of the driving signal at the low level potential of the second reference. The shift register can avoid the leakage from the first output end, decrease the raising time of the driving signal and occupy the small area.

According to one embodiment, a sensor including a first drive electrode, a second drive electrode disposed to be adjacent to the first drive electrode, a third drive electrode disposed to be adjacent to the second drive electrode, a first shift register circuit connected to the first drive electrode, a second shift register circuit connected to the first shift register circuit and the third drive electrode, and an OR circuit connected to the second drive electrode, the first shift register circuit, and the second shift register circuit.

The invention provides a gate driving circuit and a display device. The gate driving circuit is configured to drive a display panel of the display device, and includes shift registers and at least a dummy shift register. The shift registers are respectively configured to generate and output scan signals to scan lines of the display panel, the dummy shift register is configured to generate a dummy scan signal before the scan signals are generated. The dummy scan signal and the scan signals are sequentially generated.

A gate driving circuit includes first and second driving stages respectively driving first and second gate lines of a display panel. The first driving stage includes output transistors, a first control transistor controlling an electric potential of a control node in response to a signal provided from the second driving stage through an input terminal before a first gate signal is output, and a second control transistor applying a first carry signal to the input electrode of the first control transistor while the first gate signal is output.

The disclosure provides an array substrate, a touch display device and a driving method thereof. The array substrate includes a display region and a peripheral region. The display region includes a plurality of scan lines and the peripheral region comprises a gate electrode driving circuit and a touch driving circuit, the gate electrode driving circuit includes a plurality of stages of shift registers. Each of the plurality of stages of shift registers corresponds to and is electrically connected to one of the plurality of scan lines. The plurality of stages of shift registers are disposed at one side or two sides of the peripheral region. The shift registers disposed at at least one side of the peripheral region are divided into N groups of shift registers. The touch driving circuit includes N groups of touch selection outputting units corresponding to the N groups of shift registers.

A scan driver circuit for driving scanning lines is proposed. The scan driver circuit includes a pull-down control module, a pull-down module, a recovering control module, a recovering module, a downlink module, a first bootstrap capacitor, a constant low voltage supply, and a constant high voltage supply. The present inventive scan driver circuit has advantages of simple structure and low power consumption.

A display device includes: a plurality of pixels; a plurality of gate lines connected to the plurality of pixels; an output terminal connected to a gate line of the gate lines; a first transistor connected to a first node, a first clock signal input terminal and the output terminal; a second transistor connected to a second clock signal input terminal, a low-level power voltage and the output terminal; a third transistor connected to a second node, the low-level power voltage and the first node; a fourth transistor connected to a first forward input terminal, the low-level power voltage and the second node; and a fifth transistor connected to a first backward input terminal, the low-level power voltage and the second node.

A shift-register unit circuit includes a first input sub-circuit configured to have a display-input terminal to receive a display-input signal, and to provide a display output-control signal to a first node; a second input sub-circuit configured to have a blank-input terminal to receive a blank-input signal for charging a blank-control node, and to provide a blank output-control signal to the first node; an output sub-circuit configured to output signal under control of the first node; a first control sub-circuit, configured to control a voltage level of a second node under control of the first node; a second control sub-circuit configured to pull down voltage levels of the first node and the output terminal to turn-off voltage levels under control of the second node; and an anti-leak sub-circuit configured to provide a working voltage level to an anti-leak connection point.

A display device with a variant-shape display region other than the rectangular display region is configured to form a scanning line drive circuit along the variant-shape display region. The scanning line drive circuit includes bus wiring group with clock wiring for supplying clocks with three or more phases and the power supply wiring for supplying power, and the unit circuits for configuring the shift register including five or more transistors. The bus wiring and the unit circuits are formed on the different regions so as not to cross with one another.

An electronic device includes a substrate, a first transistor, a second transistor and a conductor. The first transistor is disposed on the substrate and comprises an oxide semiconductor layer. The second transistor is disposed on the substrate and comprises a silicon semiconductor layer. The conductor is electrically connected to the oxide semiconductor layer and the silicon semiconductor layer.