A shift register circuit includes a first control sub-circuit and a first output sub-circuit. The first control sub-circuit is configured to: adjust a voltage of a first node to a turn-on voltage due to an influence of a first direct current voltage signal from a first clock signal terminal, an initial voltage signal from an initial signal terminal and a second direct current voltage signal from a second clock signal terminal; and maintain the voltage of the first node at the turn-on voltage due to an influence of a first clock signal from the first clock signal terminal and a second clock signal from the second clock signal terminal. The first output sub-circuit is configured to be turned on under a control of the turn-on voltage of the first node to transmit a first voltage signal from a first voltage terminal to a signal output terminal.

A display panel includes sub-pixels and a scan driving circuit. The scan driving circuit includes a plurality of stages of shift registers including at least one first shift register and at least one second shift register, and a plurality of clock signal lines including at least one first sub-clock signal line and at least one second sub-clock signal line. Each shift register includes a first sub-circuit and a second sub-circuit. A first sub-clock signal line in the at least one first sub-clock signal line is electrically connected to a first sub-circuit in a first shift register in the at least one first shift register. A second sub-clock signal line in the at least one second sub-clock signal line is electrically connected to one sub-circuit of a first sub-circuit and a second sub-circuit in a second shift register in the at least one second shift register.

The present disclosure discloses a gate drive circuit and a display panel. The gate drive circuit includes a plurality of shift registers. Each shift register includes a level transmission signal selection module, a pull-up control module, a pulse quantity reduction module, a first inverting module, a first output module, a second output module, and a voltage boosting module. By connecting the voltage boosting module between a second electrode of a second transistor and a low potential line in series, when a first transistor is turned on, a potential of the second electrode of the second transistor can be increased, and on-state current of the second transistor can be reduced, so that a pulse amplitude of a second gate drive signal can be increased and stabilized.

The present disclosure discloses a display panel and a display device. The display panel includes a pixel circuit. The pixel circuit includes a mirror current receiving module, a digital driving module, and a light-emitting module. The mirror current receiving module includes N mirror current receiving units. A control terminal of each N mirror current receiving unit is connected to one mirror current, and the N mirror current receiving units are respectively connected in series to light-emitting subloops. N is an integer greater than or equal to 2. The digital driving module includes N digital driving units respectively connected in series to the light-emitting subloops. The light-emitting module is connected to a light-emitting loop formed by the light-emitting subloops.

Provided is a display panel. In the same shift register unit, an input module receives an input signal and a scan control signal and controls a signal of a first node; a reset module receives a reset clock signal and the scan control signal and controls a signal of a second node; an output module receives the signal of the first node, the signal of the second node, a first level signal, and an output clock signal and outputs a gate drive signal; and the refresh control module controls, according to the first refresh control signal, the time interval of the active level of the gate drive signal output by the shift register unit, and controls, according to the second refresh control signal, the time period of the inactive level of the gate drive signal output by the shift register unit.

A scan line to which a selection signal or a non-selection signal is input from its end, and a transistor in which a clock signal is input to a gate, the non-selection signal is input to a source, and a drain is connected to the scan line are provided. A signal input to the end of the scan line is switched from the selection signal to the non-selection signal at the same or substantially the same time as the transistor is turned on. The non-selection signal is input not only from one end but also from both ends of the scan line. This makes it possible to inhibit the potentials of portions in the scan line from being changed at different times.

A gate drive circuit and a display device are provided. The present disclosure pertains to the technical field of display technology and solves the technical problem of wide frame of the existing display device. The shifting register is configured to output primary drive signal into a first follower and a second follower in consecutive first scanning period t1 and second scanning period t2. The first follower is configured to output gate drive signal to a first gate line in t1 under the driving of the primary drive signal; and the second follower is configured to output the gate drive signal to a second gate line in t2 under the driving of the primary drive signal. The present disclosure can be applied to display devices, such as liquid crystal display devices and OLED display devices, and the like.

A shift register, a gate driving circuit and a display apparatus are provided. The shift register comprises a pull-up node control unit, a pull-down node control unit, a pull-up output unit, a noise reduction unit, and a touch scanning control unit. Herein, the pull-up node control unit is connected to a first input terminal, a second input terminal, a first power supply terminal, a second power supply terminal, and a pull-up node (PU); the pull-down node control unit is connected to a high level terminal (VGH), a low level terminal (VGL) and the pull-up node (PU) and a pull-down node (PD); the pull-up output unit is connected to a clock signal input terminal (CLK), the pull-up node (PU), a signal output terminal (Output); the noise reduction unit is connected to the pull-up node (PD) and the low level terminal (VGL); the touch scanning control unit is connected to a control signal input terminal (SW), the pull-up node (PU), the signal output terminal (Output), and the low level terminal (VGL).

Provided is a charging scan and charge sharing scan double output GOA circuit to combine the time sequence and circuit. The nth stage GOA unit circuit receives the first, the second low frequency clock signals (LC1, LC2), the direct current low voltage signal (Vss), the Mth, M2th high frequency clock signals (CK(M), CK(M2)), a stage transfer signal (ST(n2)) generated by the n2th stage GOA unit circuit, a charging scan signal (CG(n2)) generated by the n2th stage GOA unit circuit and a stage transfer signal (ST(n+2)) generated by the n+2th stage GOA unit circuit, the charging scan signal (CG(n)), a charge sharing scan signal (SG(n2)) generated by the n2th stage GOA unit circuit and the stage transfer signal (ST(n)) are respectively outputted with different TFTs; the nth stage GOA unit circuit comprises a transmission module (100), a transfer regulation module (200), an output module (300), a rapid pull-down module (400) and a pull-down holding module (500).

Provided is a charging scan and charge sharing scan double output GOA circuit to combine the time sequence and circuit. The nth stage GOA unit circuit receives the first, the second low frequency clock signals (LC1, LC2), the direct current low voltage signal (Vss), the Mth, M2th high frequency clock signals (CK(M), CK(M2)), a stage transfer signal (ST(n2)) generated by the n2th stage GOA unit circuit, a charging scan signal (CG(n2)) generated by the n2th stage GOA unit circuit and a stage transfer signal (ST(n+2)) generated by the n+2th stage GOA unit circuit, the charging scan signal (CG(n)), a charge sharing scan signal (SG(n2)) generated by the n2th stage GOA unit circuit and the stage transfer signal (ST(n)) are respectively outputted with different TFTs; the nth stage GOA unit circuit comprises a transmission module (100), a transfer regulation module (200), an output module (300), a rapid pull-down module (400) and a pull-down holding module (500).