The present invention provides a Gate driver on Array circuit, a display panel and a display device. The Gate driver on Array circuit comprises: shift register SR circuits of multiple stages and a signal connection circuit of the shift register SR circuits of multiple stages, and the shift register SR circuit of each stage comprises: a pre-charge controller, three thin film transistors and a capacitor; and the SR circuit of each stage further comprises: at least one switch, and a G electrode of the switch is inputted with a touch panel scan signal, and a S electrode of the switch is coupled to a K output end, and a D electrode of the switch is coupled to a scan line gate electrode signal of the SR circuit; the K output end inputs a K signal, and the K signal is synchronized with a touch panel signal TP signal.

A shift register is provided, which includes a blanking input circuit, a blanking control circuit, a blanking pull-down circuit, .[.and.]. a shift register circuit.Iadd., and a twenty-ninth transistor.Iaddend.. The blanking input circuit may provide a blanking input signal to a first control node .[.according to a second clock signal..]. .Iadd.and comprise a first transistor .Iaddend.The blanking control circuit may .[.provide a first clock signal to a second control node and maintain a voltage difference between the first control node and the second control node, according to a voltage of the first control node..]. .Iadd.comprise a second transistor. .Iaddend.The blanking pull-down circuit may provide a voltage of the second control node to a pull-down node according to .[.the.]. .Iadd.a .Iaddend.first clock signal .Iadd.and comprise a third transistor and a third leakage-preventative transistor.Iaddend.. The shift register circuit may provide a shift signal via a shift signal output terminal and a first drive signal via a first drive signal output terminal according to a voltage of the pull-down node.

An integrated circuit for transition fault testing comprises a synchronizing circuit including a first set of shift registers coupled to receive a scan enable signal and to provide a synchronizing signal based on the scan enable signal; a clock leaker circuit coupled to the synchronizing circuit and including a second set of shift registers coupled to receive a first clock signal based on the synchronizing signal and to provide a second clock signal that includes a set of pulses; and a multiplexer (MUX) that includes a first input coupled to receive a shift clock, a second input coupled to the clock leaker circuit to receive the second clock signal, and an output configured to provide an output clock signal that includes a second set of pulses.

The present disclosure provides a shift register, a gate driving circuit and a display device. The shift register comprises a set/reset unit, a pull down control unit, a pull down unit and an output unit. The set/reset unit sets or resets a pull up node in the output unit in response to a set signal or a reset signal. The output unit outputs an output signal in response to a first control signal through an output terminal of the shift register. The pull down control unit sets a pull down node in the pull down unit in response to a second control signal. The pull down control unit comprises a transistor and a capacitor, and the second control signal is applied to a gate of the transistor through the capacitor.

The present invention discloses a liquid crystal display device and a GOA scanning circuit. The GOA scanning circuit includes multiple cascaded GOA circuit units, and an n-th stage GOA circuit unit includes: a forward and backward scanning module including a first thin-film transistor and a second thin-film transistor, wherein, two current path terminals of the first thin-film transistor are respectively connected with a first clock signal and a first node; two current path terminals of the second thin-film transistor are respectively connected with a second clock signal and the first node; a control terminal of the first thin-film transistor is connected with a stage-transferring signal STn1 of a previous stage GOA circuit unit; a control terminal of the second thin-film transistor is connected with a stage-transferring signal STn+1 of a next stage GOA circuit unit.

There are provided a shift register, a gate driving circuit and a relevant display device, comprising a first node controlling module (1), a second node controlling module (2), a third node controlling module (3), a first outputting module (4) and a second outputting module (5). The first node controlling module (1) adjust a potential of a first node (A), the second node controlling module (2) adjust a potential of a second node (B), the third node controlling module (3) adjust a potential of a third node (C), the first outputting module (4) adjust a potential of a driving signal output terminal (Output), and the second outputting module (5) adjusts the potential of the driving signal output terminal (Output). Through mutual coordination of the five modules, the shift register could control a time length of a scanning signal outputted by the driving signal output terminal (Output) by only changing a time length of an input signal (Input), without changing clock signals (CK,CB) and changing the circuit and process, so that difficulty of the gate driving circuit and complexity of process could be reduced, thereby the cost is reduced.

The present disclosure provides a shift register unit including a pull-up module, an input module, a reset module, a first pull-down module, a second pull-down module, a first control module, a second control module, a first state clearing module, and a second state clearing module. The shift register unit utilizes a first clock signal and a second clock signal to cause the first and second pull-down modules to pull down alternately, in order to maintain the stability of the output signal. Furthermore, each of the TFTs in the circuit structure has a duty cycle smaller than 50%, so that the lifetime of TFTs is greatly increased. The present disclosure further provides a gate driving device and a display device using the shift register unit.

A shift register unit and a control method thereof, a gate driving circuit, and a display device. The shift register unit includes a signal input module, connected to a signal input terminal, a first clock signal terminal and a control node; a pull-down module, connected to the control node, a first voltage terminal and a signal output terminal; a first pull-up control module, connected to the control node, the pull-up module and a second voltage terminal; a second pull-up control module, connected to the control node, the pull-up module, the first clock signal terminal, the first voltage terminal and a second clock signal terminal; and a pull-up module, connected to the signal output terminal and the second voltage terminal. The problem that it is difficult to realize a narrow display frame by the bonding process due to size increase of the driving circuit can be solved.

A scan driving circuit is provided. The scan driving circuit for driving cascaded scan lines includes a scan driving circuit, a latch module, a driving-signal generation module, an output control module, a high gate voltage source, and a low level gate voltage. The scan driving circuit of the present invention conducts a driving operation for the latch module by a first cascade signal and a second cascade signal, so that a clock signal is not required to be processed with a phase inversion, and thereby the scan driving circuit has less overall power consumption.

The present invention provides a charging scan and charge sharing scan double output GOA circuit to combine the time sequence and circuit. The nth stage GOA unit circuit receives the first, the second low frequency clock signals (LC1, LC2), the direct current low voltage signal (Vss), the Mth, M2th high frequency clock signals (CK(M), CK(M2)), a stage transfer signal (ST(n2)) generated by the n2th stage GOA unit circuit, a charging scan signal (CG(n2)) generated by the n2th stage GOA unit circuit and a stage transfer signal (ST(n+2)) generated by the n+2th stage GOA unit circuit, the charging scan signal (CG(n)), a charge sharing scan signal (SG(n2)) generated by the n2th stage GOA unit circuit and the stage transfer signal (ST(n)) are respectively outputted with different TFTs; the nth stage GOA unit circuit comprises a transmission module (100), a transfer regulation module (200), an output module (300), a rapid pull-down module (400) and a pull-down holding module (500).