A scan driver includes a plurality of stages configured to supply scan signals to scan lines. An ith (i is a natural number) stage of the stages at one side of a panel includes: a first transistor connected between a first input terminal and a first node, and including a gate electrode connected to a second input terminal; a second transistor connected between a third input terminal and a first output terminal for outputting an ith scan signal of the scan signals, and including a gate electrode connected to the first node; a third transistor connected between the first output terminal and a first power input terminal configured to receive a first off voltage, and including a gate electrode connected to the second input terminal; and a first capacitor connected between the first node and the first output terminal.

Provided is a charging scan and charge sharing scan double output GOA circuit to combine the time sequence and circuit. The nth stage GOA unit circuit receives the first, the second low frequency clock signals (LC1, LC2), the direct current low voltage signal (Vss), the Mth, M2th high frequency clock signals (CK(M), CK(M2)), a stage transfer signal (ST(n2)) generated by the n2th stage GOA unit circuit, a charging scan signal (CG(n2)) generated by the n2th stage GOA unit circuit and a stage transfer signal (ST(n+2)) generated by the n+2th stage GOA unit circuit, the charging scan signal (CG(n)), a charge sharing scan signal (SG(n2)) generated by the n2th stage GOA unit circuit and the stage transfer signal (ST(n)) are respectively outputted with different TFTs; the nth stage GOA unit circuit comprises a transmission module (100), a transfer regulation module (200), an output module (300), a rapid pull-down module (400) and a pull-down holding module (500).

An organic light emitting display device includes a display panel and a stage block. The display panel includes 4m (m is a natural number) number of horizontal lines in which organic light emitting diodes (OLEDs) are arranged. The stage block provides a scan signal and an emission control signal to each of the horizontal lines. An i (i is a natural number equal to or smaller than m) stage block includes a block signal generating unit, an emission control signal generating unit, and a plurality of scan signal generating units.

A display panel and a display device. The display panel comprises: a substrate, a display area (100) provided with at least one light-emitting signal line (E), at least one first reset signal line (R) and sub-pixels arranged in an array, at least one sub-pixel (P1, P2, P3) comprising: a light-emitting device (L) and a pixel circuit. The first reset signal line (R) is configured to provide a reset control signal for the pixel circuit, the light-emitting signal line is configured to provide a light-emitting control signal for the pixel circuit to provide a driving current. For the first reset signal line and the light-emitting signal line connected to a same pixel circuit, the duration in which the signal of the light-emitting signal line is an invalid level signal is equal to the duration in which the signal of the first reset signal line is a valid level signal.

A shift-register unit circuit includes a first input sub-circuit configured to have a display-input terminal to receive a display-input signal, and to provide a display output-control signal to a first node; a second input sub-circuit configured to have a blank-input terminal to receive a blank-input signal for charging a blank-control node, and to provide a blank output-control signal to the first node, wherein the second input sub-circuit includes an isolation sub-circuit, wherein the isolation sub-circuit is set between the first node and the blank-control node; an output sub-circuit configured to output signal under control of the first node; and an anti-leak sub-circuit configured to provide a working voltage level to an anti-leak connection point. The anti-leak sub-circuit includes a second anti-leak transistor connected to the isolation sub-circuit.

A charge-coupled device (CCD) image sensor is provided. The CCD image sensor may include an array of photosensors that transfer charge to multiple vertical CCD shift registers, which then in turn transfer the charge to a horizontal CCD shift register. The horizontal CCD shift register then feeds an output buffer circuit. The output buffer circuit can include multiple output stages, each of which can include a source-follower transistor coupled in series with a current sink transistor and at least one cascode transistor. The current sink transistor may have its gate terminal shorted to ground. In one arrangement, the cascode transistor has a gate terminal that receives a non-zero bias voltage. In another arrangement, the cascode transistor has a gate terminal that is also shorted to ground and operates in depletion mode.

A circuit and an array circuit for implementing a shift operation are provided. The circuit for implementing a shift operation includes a resistive random-access memory and four switches. The circuit has a simple structure and can improve computational efficiency.

A scan driving circuit, including a multi-stage shift register unit that outputs scan signals by stage under control of a clock signal (CKR, CKBR), the shift register unit includes an output terminal for outputting the scan signals, the scan driving circuit further includes a multi-stage signal generating unit, with an n-th stage signal generating unit is connected respectively to an output terminal of an n-th stage shift register unit and an output terminal of an (n+j)-th stage shift register unit, the n-th stage signal generating unit is configured to convert an outputted first level into a second level under triggering of a scan signal outputted by the n-th stage shift register unit, and convert an outputted second level into a first level under triggering of a scan signal outputted by the (n+j)-th stage shift register unit; the n and j both are positive integers.

In accordance with an embodiment of the present disclosure, a semiconductor device may be provided. The semiconductor device may semiconductor device may be configured to store a bank address applied to an active signal from among command signals, and may perform a read or a write operation using the stored bank address based on activation of a command signal.

There are provided a shift register, a gate driving circuit and a relevant display device, comprising a first node controlling module (1), a second node controlling module (2), a third node controlling module (3), a first outputting module (4) and a second outputting module (5). The first node controlling module (1) adjust a potential of a first node (A), the second node controlling module (2) adjust a potential of a second node (B), the third node controlling module (3) adjust a potential of a third node (C), the first outputting module (4) adjust a potential of a driving signal output terminal (Output), and the second outputting module (5) adjusts the potential of the driving signal output terminal (Output). Through mutual coordination of the five modules, the shift register could control a time length of a scanning signal outputted by the driving signal output terminal (Output) by only changing a time length of an input signal (Input), without changing clock signals (CK,CB) and changing the circuit and process, so that difficulty of the gate driving circuit and complexity of process could be reduced, thereby the cost is reduced.