A flexible display panel and a driving method thereof, and a display device are provided. The flexible display panel includes a pixel region and a gate driving circuit region located outside the pixel region. The flexible display panel further includes a curvature adjusting unit located on two sides of the pixel region, the curvature adjusting unit includes a plurality of isosceles trapezoid units which are sequentially connected with each other through lower surfaces thereof, each isosceles trapezoid unit includes an upper surface, the lower surface, and a third waist surface and a fourth waist surface oppositely arranged between the upper surface and the lower surface, and a length of the upper surface between the third waist surface and the fourth waist surface is less than a length of the lower surface between the third waist surface and the fourth waist surface. In the case that the display panel is bent and in a bent portion of the display panel, the third waist surface of the isosceles trapezoid unit attaches to the fourth waist surface of the isosceles trapezoid unit adjacent thereto, and the upper surface of the isosceles trapezoid unit is connected with the upper surface of the isosceles trapezoid unit adjacent thereto.

Provided are a gate driving circuit and a display device using the same, and the gate driving circuit includes a shift register which includes stages. The n-th stage (n is a positive integer) includes an auto reset circuit that receive a first clock and a carry signal received from an (n1)-th stage, regulates a Q node to be at a low voltage when the first clock is at a high voltage and the carry signal is at a low voltage, and regulates the Q node to be at a high voltage when both of the first clock and the carry signal are at a high voltage.

The disclosure provides an array substrate, a touch display device and a driving method thereof. The array substrate includes a display region and a peripheral region. The display region includes a plurality of scan lines and the peripheral region comprises a gate electrode driving circuit and a touch driving circuit, the gate electrode driving circuit includes a plurality of stages of shift registers. Each of the plurality of stages of shift registers corresponds to and is electrically connected to one of the plurality of scan lines. The plurality of stages of shift registers are disposed at one side or two sides of the peripheral region. The shift registers disposed at at least one side of the peripheral region are divided into N groups of shift registers. The touch driving circuit includes N groups of touch selection outputting units corresponding to the N groups of shift registers.

A display is disclosed. The display comprises a panel, a data driver and a scan driver. The panel comprises pixels, data lines and scan lines. The data lines transmit data signals to the pixels, and the scan lines transmit scan signals to the pixels. The data driver provides the data signals, and the scan driver provides the scan signals. The scan driver comprises a shift register circuit. The shift register circuit comprises an i+1.sup.th stage carry shift register, an i.sup.th stage carry shift register and a j.sup.th stage buffer shift register. The i.sup.th stage carry shift register generates an i+1.sup.th start signal to start the i+1.sup.th stage carry shift register, so that the i+1.sup.th stage carry shift register generates an i+2.sup.th start signal. The i+1.sup.th start signal starts the j.sup.th stage buffer shift register to generate a j.sup.th output signal.

An output control node stabilization portion includes a thin film transistor having a gate terminal to which is provided a fourth clock that changes to an on level at timing at which a scanning signal outputted from a previous stage is to change from an off level to an on level, a drain terminal connected to an output control node, and a source terminal to which the scanning signal outputted from the previous stage is provided; and a thin film transistor having a gate terminal to which is provided a third clock that changes to an on level at timing at which a scanning signal outputted from a subsequent stage is to change from an off level to an on level, a drain terminal connected to the output control node, and a source terminal to which the scanning signal outputted from the subsequent stage is provided.

The present invention provides a multi-phase clock generating circuit and liquid crystal display panel, said circuit comprising: a shift register including N shift registration units, which are cascaded with each other; a first output terminal of nth shift registration units connected to a first input terminal of an (n+1)th shift registration unit; a thin film transistor set including N thin film transistors, said control terminals of said thin film transistors of a nth stage are respectively connected to said first output terminals of (Nn+1) shift registration units.

A liquid crystal display device includes a plurality of pixel units, an electrode line surrounding the pixel units, at least one gate driver coupled with the pixel units via a plurality of gate lines, and at least one electrostatic discharge protection circuit coupled with the at least one gate driver and the electrode line.

A gate driving unit, a gate driving circuit, a driving method thereof, and a display device are disclosed. The gate driving unit includes first to eighth transistors, a first capacitor and a second capacitor. The gate driving circuit includes multiple gate driving units arranged along a first direction, of which first timing control signal terminals and second timing control signal terminals of respective stages are electrically connected to a first lead terminal and a second lead terminal respectively. In addition, the gate driving circuit is driven along the first direction or along a second direction in reset periods and shift periods. The display device includes a display region and a frame region surrounding the display region, where a portion of the frame region on at least one side of the display region is provided with a gate driving circuit.

A scan line driver is disclosed. In one aspect, the scan line driver includes a driving signal generation circuit, an output line driving circuit, and a carry transfer circuit. The driving signal generation circuit is configured to generate first and second driving signals based on a plurality of clock signals and a carry signal from a previous scan line driver. The output line driving circuit is configured to generate a scan line enable signal based on the first and second driving signals. The carry transfer circuit is configured to generate a carry signal based on the first and second driving signals.

A display device with a variant-shape display region other than the rectangular display region is configured to form a scanning line drive circuit along the variant-shape display region. The scanning line drive circuit includes bus wiring group with clock wiring for supplying clocks with three or more phases and the power supply wiring for supplying power, and the unit circuits for configuring the shift register including five or more transistors. The bus wiring and the unit circuits are formed on the different regions so as not to cross with one another.