A scan driving circuit is provided. The scan driving circuit for driving cascaded scan lines includes a scan driving circuit, a latch module, a driving-signal generation module, an output control module, a high gate voltage source, and a low level gate voltage. The scan driving circuit of the present invention conducts a driving operation for the latch module by a first cascade signal and a second cascade signal, so that a clock signal is not required to be processed with a phase inversion, and thereby the scan driving circuit has less overall power consumption.

The present invention discloses a gate drive circuit and a shift register. The gate drive circuit comprises a plurality of shift register circuits which are cascade connected, and each of the shift register circuits comprises a clock control transmission circuit and a NOR gate latch circuit, wherein the clock control transmission circuit is triggered by a first clock pulse of a clock signal to transmit a gate drive pulse of a former stage to the NOR gate latch circuit, and the NOR gate latch circuit performs latch, and the NOR gate latch circuit is further triggered by a second clock pulse following the first clock pulse to output the gate drive pulse. With the aforesaid arrangement, the gate drive circuit of the present invention is applicable to CMOS process, and the power consumption is low and the noise margin is wide.

A data transfer circuit has a first data transmission unit and two or more second shift registers. The first data transmission unit has a first shift register which has a plurality of first flip flop circuits which store data, shifts the data of the plurality of first flip flop circuits, and transmits data of two or more output terminals out of output terminals of the plurality of first flip flop circuits to the two or more second shift registers. The two or more second shift registers each shift data inputted from the two or more output terminals out of the output terminals of the plurality of first flip flop circuits.

A scan line to which a selection signal or a non-selection signal is input from its end, and a transistor in which a clock signal is input to a gate, the non-selection signal is input to a source, and a drain is connected to the scan line are provided. A signal input to the end of the scan line is switched from the selection signal to the non-selection signal at the same or substantially the same time as the transistor is turned on. The non-selection signal is input not only from one end but also from both ends of the scan line. This makes it possible to inhibit the potentials of portions in the scan line from being changed at different times.

A semiconductor device includes first and second transistors having the same conductivity type and a circuit. One of a source and a drain of the first transistor is electrically connected to that of the second transistor. First and third potentials are supplied to the circuit through respective wirings. A second potential and a first clock signal are supplied to the others of the sources and the drains of the first and second transistors, respectively. A second clock signal is supplied to the circuit. The third potential is higher than the second potential which is higher than the first potential. A fourth potential is equal to or higher than the third potential. The first clock signal alternates the second and fourth potentials and the second clock signal alternates the first and third potentials. The circuit controls electrical connections between gates of the first and second transistors and the wirings.

The present invention provides a liquid crystal display that can reduce occurrence of quality problems and improve adhesive strength between substrates. The present invention is a liquid crystal display including a first substrate, a second substrate, and a seal. The first substrate includes a shift register monolithically formed on an insulating substrate, a plurality of bus lines, a first end, and a display region. The shift register includes a plurality of multistage-connected unit circuits and wiring connected to the plurality of unit circuits, and is arranged in a region between the first end and the display region. At least one of the unit circuits includes a clock terminal, an output terminal, an output transistor, a second transistor, and a bootstrap capacitor. The output transistor and the bootstrap capacitor are arranged in a region between the first end and one of the wiring and the second transistor.

An electronic device includes a substrate, a first transistor, a second transistor, an electronic unit and a conductor. The first transistor is disposed on the substrate and comprises a first semiconductor layer. The second transistor is disposed on the substrate and comprises a second semiconductor layer, wherein a material of the first semiconductor layer is different from a material of the second semiconductor layer. The electronic unit is disposed on the substrate and electrically connected to the second transistor. The conductor is electrically connected to the first semiconductor layer and the second semiconductor layer.

A display substrate, includes: a base substrate; light-emitting elements located in a display area; pixel driving circuits located respectively connected to the light-emitting elements, each pixel driving circuit including an N-type transistor and a P-type transistor; a first gate driving circuit, a second gate driving circuit and a third gate driving circuit in a border area of the display area, the first and third gate driving circuits being connected with the P-type transistor, the second gate driving circuit being connected with the N-type transistor, and orthographic projections of the first to third gate driving circuits on the base substrate are not overlapped with each other; orthographic projections of adjacent boundary areas of the first and second gate driving circuits on the base substrate are at least partially nested; and a planarization layer located between the pixel driving circuits and the light-emitting elements.

A first flipflop outputs a first signal synchronized with a first clock signal. In the first transistor, the first clock signal is input to a first terminal and the second signal is output from a second terminal. In the fourth transistor, a first signal is input to a first terminal and a second terminal is electrically connected to a gate of the first transistor. In the sixth transistor, the third signal is input to a first terminal, a second terminal is electrically connected to the gate of the fourth transistor, and the gate of the sixth transistor is electrically connected to the first terminal.

The present application provides a gate drive circuit, a drive device and a display device. The gate drive circuit includes m switch groups, n first shift registers and m second shift registers. Each switch group includes n first switch units. The n first shift registers cyclically output a first row-scan signal, while each second shift register controls the n first switch units connected to each first controlled node corresponding to the second shift register to be turned on, so that the first row-scan signal is fed back to each gate-line in turn, to realize a line-by-line scan driver. The gate drive circuit only needs n+m shift registers to complete the gate drive, compared with the existing gate drive circuit requiring nm shift registers, the number of shift registers is reduced, the cost is reduced and the manufacturing process is simplified.