The present application discloses a display panel, a display panel driving method and a display device, where the display panel includes: a driving circuit; the driving circuit includes a plurality of shift register units; the shift register unit includes a driving control module, a stage transmission module and a scanning module; the driving control module includes a starting input end, a scanning control end, a first node and a second node; the stage transmission module includes a first input end, a second input end, a first level end, a stage transmission clock end and a stage transmission output end; the first input end is electrically connected to the first node, and the second input end is electrically connected to the second node.

A gate drive circuit and a display device are provided, wherein the gate drive circuit includes cascaded shift registers. In each shift register, a scan output terminal is electrically connected to a scan signal line, and a pull-down module transmits a voltage of a power node to the scan output terminal when the pull-down module is conducting. In odd-numbered rows, the power node electrically connects a first detection signal line, while in even-numbered rows, the power node electrically connects a second detection signal line. When the gate drive circuit is in a driving state, the first detection signal line and the second detection signal line transmit a first voltage to the scan signal lines when the pull-down modules are conducting.

A display substrate includes: a base substrate; light-emitting elements located in a display area; pixel driving circuits located respectively connected to the light-emitting elements, each pixel driving circuit including an N-type transistor and a P-type transistor; a first gate driving circuit, a second gate driving circuit and a third gate driving circuit in a border area of the display area, the first and third gate driving circuits being connected with the P-type transistor, the second gate driving circuit being connected with the N-type transistor, and orthographic projections of the first to third gate driving circuits on the base substrate are not overlapped with each other; and a planarization layer located between the pixel driving circuits and the light-emitting elements.

The present disclosure discloses a display panel and a display device. The display panel includes a pixel circuit. The pixel circuit includes a mirror current receiving module, a digital driving module, and a light-emitting module. The mirror current receiving module includes N mirror current receiving units. A control terminal of each N mirror current receiving unit is connected to one mirror current, and the N mirror current receiving units are respectively connected in series to light-emitting subloops. N is an integer greater than or equal to 2. The digital driving module includes N digital driving units respectively connected in series to the light-emitting subloops. The light-emitting module is connected to a light-emitting loop formed by the light-emitting subloops.

A shift register unit includes: an input circuit configured to provide an input signal to a first node in response to a first clock signal; a reset circuit configured to provide a first reference signal to a second node in response to a second clock signal; a first control circuit configured to provide the second clock signal to the second node in response to a first control signal; an output circuit configured to provide a third clock signal to a drive output terminal in response to a signal of the first node, and provide a second reference signal to the drive output terminal in response to a signal of the second node; where a duration of an active level of the first control signal is longer than a duration of an active level of a signal of the drive output terminal.

A gate driving circuit and a display panel are provided. A gate driving unit in the gate driving circuit includes a pull-up control module, a pull-up node, a pull-down control module, a pull-down node, and a pull-down module. The pull-up control module is electrically connected to the pull-up node. The pull-down control module is electrically connected to the pull-down node. The pull-down control module is electrically connected to a scanning signal input terminal of a previous one stage gate driving unit or a scanning signal input terminal of a previous two stage gate driving unit. The pull-down module is electrically connected to the pull-up node and the pull-down node.

A gate driving circuit includes a first gate driving circuit and a second gate driving circuit. The first driving circuit includes 1.sup.st to N.sup.th first shift registers that are configured to output 1.sup.st to N.sup.th first scan signals to N number of scan lines, respectively. The second driving circuit includes 1.sup.st to N.sup.th second shift registers that are configured to output 1.sup.st to N.sup.th second scan signals to the other N number of scan lines, respectively. The number of transistors in each of the 1.sup.st to N.sup.th second shift registers is less than the number of transistors in each of the 1.sup.st to N.sup.th first shift registers.

Disclosed are a display substrate and a display apparatus, wherein the display substrate includes a display region and a non-display region which includes a rounded corner region; the display substrate includes a circuit structure layer including a pixel circuit and a control drive circuit; the circuit structure layer further includes a plurality of reset output lines and a plurality of reset transfer lines located in the non-display region and disposed on a side of the control drive circuit close to the display region, and an extension direction of the reset output line and an extension direction of the reset transfer line intersect; the reset transfer line is connected with the pixel circuit; an orthographic projection of at least one reset transfer line located in the rounded corner region on the base substrate is partially overlapped with orthographic projections of the plurality of reset output lines on the base substrate.

A shift register includes a shift module configured for causing the cascade signal output end to output a cascade signal in response to a signal of the input signal end; an reverse output module configured for causing the reverse signal output end to output a signal reverse to the cascade signal output end in response to a signal of the cascade signal output end; a latch module configured for causing an output end of the latch module to output a control signal of the masking signal end in response to signals of the cascade signal output end and the reverse signal output end of a previous level; and a selection output module configured for providing a signal of the first power supply end or the second power supply end to the driving signal output end in response to a signal of the output end of the latch module.

An integrated circuit die stack and method thereof are described herein that is capable of detecting a physical tampering event. The integrated circuit die stack includes a first integrated circuit die including a sensor network that extends substantially across an entire top surface of the first integrated circuit die, and a second integrated circuit die stacked below the first integrated circuit die. The second integrated circuit die is configured to receive sensing signals generated by the sensor network via a plurality of through-silicon-vias coupled with the first integrated circuit die and the second integrated circuit die.