A scan circuit is provided. The scan circuit includes a plurality of scan units. A respective scan unit of the plurality of scan units includes a plurality of transistors. A respective gate electrode of a respective transistor of the plurality of transistors includes a first portion and a second portion in different layers. First portions of respective gate electrodes of the plurality of transistors in the respective scan unit are configured to be provided with a power supply signal. Second portions of the respective gate electrodes of the plurality of transistors in the respective scan unit are configured to be provided with gate scanning signals, respectively. First portions of gate electrodes of at least two transistors in the respective scan unit are parts of a unitary structure.

The present application discloses a shift register, a display panel and a display device, where the shift register includes N cascaded shift register units, each of which includes an input module, a noise reduction module, a pull-down control module, a pull-down module and an output module; where in the same shift register unit, the input module is configured to receive an input signal and control a signal of a first node; the noise reduction module is configured to receive the input signal and a first level signal, and control a transmission path of the first level signal to a second node; the pull-down control module is configured to receive a first clock signal and control a signal of the second node; the output module is configured to receive a second clock signal and a signal of the first node and control a gate drive signal.

A shift register, a driver circuit, a display panel, and a display apparatus. In the shift register, a first input unit is configured to write a signal into a first node; a first output unit includes a control terminal coupled to the first node, a first terminal receiving a first voltage signal, and a second terminal coupled to a signal output terminal; a second input unit is configured to write a signal into a second node; a second output unit includes a control terminal coupled to the second node, a first terminal receiving a first clock signal, and a second terminal coupled to the signal output terminal; a holding unit includes an output terminal coupled to the second node, and is configured to maintain a potential of the second node at least during a period when the first output unit is off and the second output unit is on.

Disclosed a display device and a method of driving the same. Each of sub-pixels in the display device includes: a light-emitting element; a driving element; a first switch element; a second switch element; a third switch element; and a fourth switch element. A gate signal includes: a first-first scan signal applied to a gate electrode of the fourth switch element, a first-second scan signal applied to a gate electrode of the third switch element, a second scan signal applied to a gate electrode of the second switch element, and an emission control signal applied to a gate electrode of the first switch element. A pulse of the first-first scan signal has the same pulse width as a pulse of the first-second scan signal and precedes the pulse of the first-second scan signal.

A gate driving circuit includes stages, where each stage of the gate driving circuit includes a second transistor connected between a first node and a second node and which includes a first gate connected to a second terminal through which a first voltage is supplied and a second gate connected to a third terminal through which a second voltage is supplied, a fourth transistor connected between the second terminal and an output terminal and which includes a first gate connected to the second node and a second gate connected to the third node, a first capacitor connected between the second node and the output terminal and a second capacitor connected between the third node and the output terminal.

A display substrate includes a base substrate including a display area and a peripheral area on at least one side of the display area; a pixel array, located in the display area and including multiple pixel units; and, a scan driving module, located in a driving circuit area of the peripheral area, and including multiple shift register units, multiple signal lines being arranged in one shift register units, and extending along a first direction; wherein a ratio of a sum W1 of widths of the multiple signal lines in a second direction to a width W2 of the shift register unit in the second direction is W1/W2, and a length of at least one pixel unit along the first direction is a pixel pitch value; the first direction intersects the second direction; a product of W1/W2 and the pixel pitch value is greater than 18 um and less than 40 um.

A shift register unit includes a driving control module configured to receive an input signal and control a signal of a first output node and a signal of a second output node, a stage transfer module configured to receive a signal of a first output node and a signal of a second output node and control a stage transfer signal, a transmission control module configured to receive a stage transfer signal and a transmission control signal and control a signal of a third output node, an auxiliary control module configured to receive a signal of a second output node, a signal of a third output node and an auxiliary control signal and control a signal of a fourth output node, and a scanning module configured to receive at least a signal of a third output node and a signal of a fourth output node and control a scanning signal.

The present disclosure relates to the field of display, and discloses a shifting register, a driving method, a gate driving circuit and a display device. The shifting register includes: an input sub-circuit, coupled to a signal input terminal, a first clock signal terminal and a first node; a control sub-circuit, coupled to the first clock signal terminal, a second clock signal terminal, the signal input terminal, a first power terminal, a second power terminal and a second node, where the first power terminal or the second power terminal determines a potential of the second node under the control of the first clock signal terminal, the second clock signal terminal and the signal input terminal; and an output sub-circuit, coupled to the first power terminal, the second power terminal, the first node, the second node and a signal output terminal.

A transistor whose channel region includes an oxide semiconductor is used as a pull down transistor. The band gap of the oxide semiconductor is 2.0 eV or more, preferably 2.5 eV or more, more preferably 3.0 eV or more. Thus, hot carrier degradation in the transistor can be suppressed. Accordingly, the circuit size of the semiconductor device including the pull down transistor can be made small. Further, a gate of a pull up transistor is made to be in a floating state by switching of on/off of the transistor whose channel region includes an oxide semiconductor. Note that when the oxide semiconductor is highly purified, the off-state current of the transistor can be 1 aA/m (110.sup.18 A/m) or less. Therefore, the drive capability of the semiconductor device can be improved.

A gate driver circuit includes multiple stages of shift registers. These shift registers are cascade connected in series. Each stage of the shift registers includes a scan unit, a control unit and an output unit. The scan unit receives an enable signal. The scan unit is triggered by a clock signal to sample the enable signal, so as to generate a first node voltage. The first node voltage is utilized as a shift output signal transmitted to a subsequent shift register. The control unit receives a multiple-area-frame-rate control signal. According to the multiple-area-frame-rate control signal, the control unit selectively blocks the first node voltage and outputs the second node voltage. The output unit selectively transmits or suspends transmitting gate driver signals to a pixel circuit on a display panel according to the second node voltage.