Systems and methods of screening memory cells by modulating bitline and/or wordline voltage. In a read operation, the wordline may be overdriven or underdriven as compared to a nominal operating voltage on the wordline. In a write operation, the one or both of the bitline and wordline may be overdriven or underdriven as compared to a nominal operating voltage of each. A built-in self test (BIST) system for screening a memory array has bitline and wordline margin controls to modulate bitline and wordline voltage, respectively, in the memory array.

Embodiments provide a scheme for non-parametric PV-level modeling and an optimal read threshold voltage estimation in a memory system. A controller is configured to: generate multiple optimal read threshold voltages corresponding to multiple sets of two cumulative distribution function (CDF) values, respectively; perform read operations on the cells using a plurality of read threshold voltages; generate cumulative mass function (CMF) samples based on the results of the read operations; receive first and second CDF values, selected from among a plurality of CDF values, each CDF value corresponding to each CMF sample; and estimate an optimal read threshold voltage corresponding to the first and second CDF values, among the multiple optimal read threshold voltages.

A system and method for read threshold calibration in a non-volatile memory are provided. Physical dies in the memory are divided into groups based on device-level parameters such as time and temperature parameters. An outlier die may be identified outside of the plurality of groups based on a comparison of a bit error rate (BER) indicator for each die to a threshold. For each group of dies, a read parameter is determined for at least one die, and applied to each of the plurality of dies of the group. The read parameter may be determined based on a threshold measurement of a representative one or more word lines.

One or more sampling parameters of an application associated with a downstream voltage regulator may be determined. A power supply rejection ratio (“PSRR”) and a switching frequency of an upstream voltage regulator may be dynamically adjusted based on the sampling parameters of the application associated with the downstream voltage regulator. The sampling parameters may include a noise level and a workload of the selected application.

Methods, systems, and devices related to an improved driver for non-binary signaling are described. A driver for a signal line may include a set of drivers of a first type and a set of drivers of a second type. When the driver drives the signal line using multiple drivers of the first type, at least one additional driver of the first type may compensate for non-linearities associated with one or more other drivers of the first type, which may have been calibrated at other voltages. The at least one additional driver of the first type may be calibrated for use at a particular voltage, to compensate for non-linearities associated with the one or more other drivers of the first type as exhibited at that particular voltage.

A cache read method of a nonvolatile memory device including a plurality of page buffer units and cache latches, each page buffer units having a sensing latch and a sensing node line is provided. The method comprises performing a first on-chip valley search (OVS) read on a selected memory cell using a first sensing node line and a first sensing latch of a first page buffer unit of the plurality of page buffer units; storing first data sensed from the selected memory cell in the first sensing latch, the first data based on a result of the first OVS read; dumping the first data to sensing node lines of at least one page buffer unit, excluding the first page buffer unit, from among the plurality of page buffer units; and performing a second OVS read on the selected memory cell using the first sensing latch.

According to one embodiment, a memory system includes a semiconductor memory and a controller. The memory system is capable of executing a first operation and a second operation. In the first operation, the controller issues a first command sequence, the semiconductor memory applies a first voltage to a first word line and applies a second voltage to a second word line to read data from the first memory, and the read data is transmitted to the controller from the semiconductor memory. In the second operation, the controller issues a second command sequence, the semiconductor memory applies a third voltage to the first word line and applies a fourth voltage to the second word line, and data held in the memory cell array is left untransmitted to the controller.

A method can include, in an integrated circuit device: at a unidirectional command-address (CA) bus having no more than four parallel inputs, receiving a sequence of no less than three command value portions; latching each command value portion in synchronism with rising edges of a timing clock; determining an input command from the sequence of no less than three command value portions; executing the input command in the integrated circuit device; and on a bi-directional data bus having no more than six data input/outputs (IOs), outputting and inputting sequences of data values in synchronism with rising and falling edges of the timing clock. Corresponding devices and systems are also disclosed.

The present disclosure is drawn to, among other things, a method for accessing memory using dual standby modes, the method including receiving a first standby mode indication selecting a first standby mode from a first standby mode or a second standby mode, configuring a read bias system to provide a read bias voltage and a write bias system to provide approximately no voltage, or any voltage outside the necessary range for write operation, based on the first standby mode, receiving a second standby mode indication selecting the second standby mode, and configuring the read bias system to provide at least the read bias voltage and the write bias system to provide a write bias voltage based on the second standby mode, the read bias voltage being lower than the write bias voltage.

Techniques for estimating raw bit error rate of data stored in a group of memory cells are described. Encoded data is read from a group of memory cells. A first population value is obtained based on a first number of memory cells in the group of memory cells having a read voltage within a first range of read voltages, each read voltage representing one or more bits of the encoded data. An estimated raw bit error rate of the data is determined to satisfy a first threshold. The determination is made using a first trained machine learning model and based in part on the first population value. A first media management operation is initiated in response to the determination that the estimated raw bit error rate satisfies the first threshold.