A data input buffer includes a plurality of buffer units configured to receive a first impedance calibration code and a second impedance calibration code, wherein each of the plurality of buffer units outputs an offset detected with a first input terminal and a second input terminal thereof short-circuited, as write data, and wherein a buffer unit corresponding to a current value of the first impedance calibration code among the plurality of buffer units is configured to correct the offset according to the second impedance calibration code.

A memory device of a memory module includes a CA buffer that receives a command/address (CA) signal through a bus shared by a memory device different from the memory device of the memory module, and a calibration logic circuit that identifies location information of the memory device on the bus. The memory device recognizes its own location on a bus in a memory module to perform self-calibration, and thus, the memory device appropriately operates even under an operation condition varying depending on a location in the memory module.

Disclosed are a memory device that performs offset calibration and a method of operating the memory device. The memory device includes an input/output pad configured to receive data from a device external, an on-die termination (ODT) circuit connected to the input/output pad, a plurality of receivers connected to the ODT circuit and configured to receive the data from the input/output pad, an offset calibration circuit configured to perform an offset calibration operation on data output from the plurality of receivers and output an offset correction, a first switch configured to provide a first voltage to the plurality of receivers, and a second switch configured to provide a second voltage to the plurality of receivers. During the offset calibration operation, the plurality of receivers receive a third voltage in response to the ODT circuit being enabled and the first voltage through the first switch.

A method for performing read training of a memory channel includes writing a data pattern to a memory using a data bus having a predetermined number of bit lanes. An edge of a read data eye is determined individually for each bit lane by reading the data pattern over the data bus using a read bust cycle having a predetermined length, grouping data received on each bit lane over the read burst cycle to form a bit lane data group, and comparing the bit lane data group to corresponding expected data of the data pattern for each bit lane, logging a phase of each bit lane on which said edge is found, and repeating the reading, grouping, comparing, and logging until the edge is found for all of the bit lanes.

To reduce a measurement time, an inspection device includes a stage configured to fix a magnetoresistive random access memory (MRAM) to a stage surface and moving the MRAM, a plurality of magnets configured to generate a gradient magnetic, a plurality of line sensors comprising a first line sensor for detecting a magneto-optical effect at a first location of the MRAM and a second line sensor for detecting the magneto-optical effect at a second location that is different from the first location by moving a location of the MRAM within the gradient magnetic field, and an information processor configured to process the magneto-optical effect detected by the plurality of line sensors. Thus, throughput may be improved.

An apparatus is described. The apparatus includes a data buffer chip having write leveling training circuitry. The write leveling training circuitry to detect when a sampled value of a WL pulse within a memory chip has changed. Another apparatus is described. The other apparatus includes a registering clock driver (RCD) chip having write leveling training circuitry to determine when to send a write command to a memory chip and a data buffer chip during an external write leveling training process for the memory chip.

A circuit device 10 includes a register 30, an access control circuit 20 that controls access to a nonvolatile memory 70 and loads setting data of the circuit device 10 stored in the nonvolatile memory 70 in the register 30, and an error detection circuit 40. The access control circuit 20 performs a refresh operation that reloads the setting data stored in the nonvolatile memory 70 in the register 30. The error detection circuit 40 reads data for comparison that has been reloaded in the register 30 from the register 30, compares the data for comparison that was read with an expected value of the data for comparison, and performs access control error detection based on the comparison result.

A signal modulation apparatus, a memory storage apparatus, and a signal modulation method are disclosed. The signal modulation apparatus includes an observation circuit, a signal modulation circuit, and a phase control circuit. The signal modulation circuit is configured to generate a second signal according to a first signal and a reference clock signal. A frequency of the first signal is different from a frequency of the second signal. The phase control circuit is configured to obtain an observation information via the observation circuit. The observation information reflects a process variation of at least one electronic component in the signal modulation apparatus. The phase control circuit is further configured to control an offset between the first signal and the reference clock signal according to the observation information.

Methods, systems, and devices for monitoring and adjusting access operations at a memory device are described to support integrating monitors or sensors for detecting memory device health issues, such as those resulting from device access or wear. The monitoring may include traffic monitoring of access operations performed at various components of the memory device, or may include sensors that may measure parameters of components of the memory device to detect wear. The traffic monitoring or the parameters measured by the sensors may be represented by a metric related to access operations for the memory device. The memory device may use the metric (e.g., along with a threshold) to determine whether to adjust a parameter associated with performing access operations received by the memory device, in order to implement a corrective action.

Methods, systems, and devices for status check using signaling are described. A memory system may receive ready signals from memory dies. The ready signal may indicate whether a memory die is available to receive a command. The memory system may generate an indicator of whether the memory die is available based on values of ready signals. The memory system may output the indicator to a controller over one or more pins based on generating the indicator.