A system and method for optimizing a memory sub-system to compensate for memory device degradation. An example system including a memory controller operatively coupled with a memory device and configured to perform operations comprising: updating a setting of the memory device, wherein the setting changes a duty cycle of a signal of the memory device and comprises a first value for a first configuration and comprises a second value for a second configuration; storing error data that indicates errors when using the first configuration and errors when using the second configuration; determining a value for the setting based on the error data, wherein the determined value minimizes errors associated with the memory device; and storing the determined value for the setting of the memory device.

In a chip-to-chip signaling system includes at least one signaling link coupled between first and second ICs, the first IC has an interface coupled to the signaling link and timed by a first interface timing signal. The second IC has an interface coupled to the signaling link and timed by a second interface timing signal that is mesochronous with respect to the first interface timing signal. The second IC further has phase adjustment circuitry that adjusts a phase of the second interface timing signal using a digital counter implemented with Josephson-junction circuit elements.

Various implementations described herein refer to a device having an address bus that provides multi-port addresses from multiple ports including a first address from a first port and a second address from a second port. The device may have column contention-detection circuitry that receives the multi-port addresses from the address bus, compares the first address from the first port with the second address from the second port and provides a contention adjustment signal based on the comparison between the first address and the second address. The device may have bitline collision circuitry that receives the contention adjustment signal, senses wire-to-wire variation related to bitline coupling effects and provides a bitline collision signal based on sensing the bitline coupling effects.

A write operation assist circuit is provided, including: pre-charging circuit, a drive signal circuit, a programmable delay circuit, a charge pump, a write driving circuit and a column selector, wherein the pre-charging circuit has a pre-charging signal output terminal coupled to a pre-charging signal input terminal of the drive signal circuit, a first voltage output terminal coupled to a first bit line, and a second voltage output terminal coupled to a second bit line; the driving signal circuit has a first input terminal coupled to the first bit line, a second input terminal coupled to the second bit line, a first output terminal coupled to a first input terminal of the programmable delay circuit, and a second output terminal coupled to a second input terminal of the programmable delay circuit; the programmable delay circuit has an output terminal coupled to a first terminal of the charge pump.

An integrated circuit includes a drivability control circuit and a data output circuit. The drivability control circuit is configured to generate a drivability control signal based on data patterns of a plurality of pieces of data. The data output circuit is configured to control drivability, which is reflected to each of the plurality of pieces of data, based on the drivability control signal.

Methods, systems, and apparatuses related to memory operation with common clock signals are provided. A memory device or system that includes one or more memory devices may be operable with a common clock signal without a delay from switching on-die termination on or off. For example, a memory device may comprise first impedance adjustment circuitry configured to provide a first impedance to a received clock signal having a clock impedance and second impedance adjustment circuitry configured to provide a second impedance to the received clock signal. The first impedance and the second impedance may be configured to provide a combined impedance about equal to the clock impedance when the first impedance adjustment circuitry and the second impedance adjustment circuitry are connected to the received clock signal in parallel.

Devices and techniques are disclosed herein to extend a range of an effective delay of a delay circuit having a configurable delay limited to a first range of delay values with respect to a first edge of a clock signal. A selection circuit can selectively apply the configurable delay to a subsequent, second edge of the clock signal to extend the range of the effective delay of the delay circuit beyond the first range of delay values.

A memory device includes: first power pins in a first power area and configured to receive a first power voltage; data pins configured to transmit or receive data signals, the data pins being arranged in a first region and in a second region each including the first power area; control pins configured to transmit or receive control signals in the first region and in the second region; second power pins in a second power area between the first region and the second region and configured to receive a second power voltage different from the first power voltage; and ground pins in the second power area and configured to receive a ground voltage.

Methods, systems, and devices for timing chains for accessing memory cells are described to implement some delays at logic circuitry under an array of memory cells. The memory array logic may represent CMOS under array logic circuitry. A bank group logic may generate a first memory operation and a longer delay corresponding to a timing between the first operation and a second operation. The first operation may represent an access operation, a precharging operation, or the like. The memory array logic may be signaled regarding the first operation and may generate one or more smaller delays associated with one or more sub-operations of the first operation. The smaller delays may be tunable, which may support a memory device or controller to implement operations or sub-operations with different timings based on different processes, different memory cell characteristics, or different temperatures, among other examples.

A device and method of clock synchronization for external memory interface. The device, and method, generating a clock output from a phase lock loop block via a sub-module clocking component; multiplexing the clock output through a global clock into different clock domains; clocking the data and an address or a command path by each clock domain; clocking the phase compensation FIFO by clock domain and clock phase alignment clock; generating the pointer for the phase compensation FIFO from central pointer generator block; and synchronizing the pointer of the adjacent intellectual property module with a parent intellectual property module.