An operating method of a nonvolatile memory device for programming multi-page data, the operating method including: receiving the multi-page data from a memory controller; programming first page data among the multi-page data to first memory cells connected to a word line adjacent to a selected word line; reading previous page data previously stored in second memory cells connected to the selected word line based on a first sensing value and a second sensing value after programming the first page data; calculating a first fail bit number by comparing first bits of the previous page data read based on the first sensing value to second bits of the previous page data read based on the second sensing value; and programming the previous page data read from the second memory cells and second page data among the multi-page data to the second memory cells based on the first fail bit number.

A memory controller includes, in one embodiment, a memory interface and a controller circuit. The memory interface is configured to interface with a memory interface configured to interface with a memory having a plurality of memory blocks. Each memory block has a plurality of strings. The controller circuit is configured to perform a string defect leakage check on one of the memory blocks during a first programming operation of the one memory block, determine whether the one memory block has one or more string to string shorts based on the string defect leakage check, and resolve the string to string shorts in response to determining that the one of the memory blocks has the string to string shorts.

A nonvolatile memory device includes a memory cell array having cell strings that each includes memory cells stacked on a substrate in a direction perpendicular to the substrate. A row decoder is connected with the memory cells through word lines. The row decoder applies a setting voltage to at least one word line of the word lines and floats the at least one word line during a floating time. A page buffer circuit is connected with the cell strings through bit lines. The page buffer senses voltage changes of the bit lines after the at least one word line is floated during the floating time and outputs a page buffer signal as a sensing result. A counter counts a number of off-cells in response to the page buffer signal. A detecting circuit outputs a detection signal associated with a defect cell based on the number of off-cells.

Methods, systems, and devices for word line capacitance balancing are described. A memory device may include a set of memory tiles, where one or more memory tiles may be located at a boundary of the set. Each boundary memory tile may have a word line coupled with a driver and a subarray of memory cells, and may also include a load balancing component (e.g., a capacitive component) coupled with the driver. In some examples, the load balancing component may be coupled with an output line of the driver (such as a word line) or an input of the driver (such as a line providing a source signal). The load balancing component may adapt a load output from the driver to the subarray of memory cells such that the load of the memory tile at the boundary may be similar to the load of other memory tiles not at the boundary.

An integrated circuit includes a TSV extending from a first surface of a semiconductor substrate to a second surface of the semiconductor substrate and having a first end and a second end, and a non-volatile repair circuit. The non-volatile repair circuit includes a one-time programmable (OTP) element having a programming terminal, wherein in response to an application of a fuse voltage to the programming terminal, the OTP element electrically couples the first end of the TSV to the second end of the TSV.

A semiconductor device includes a controller circuit and a signal generating circuit. The controller circuit is coupled to a plurality of memory devices and configured to generate a plurality of chip enable signals. One of the chip enable signals is provided to one of the memory devices, so as to respectively enable the corresponding memory device. The signal generating circuit is disposed outside of the controller circuit and configured to receive the chip enable signals and generate a termination circuit enable signal according to the chip enable signals. The termination circuit enable signal is provided to the memory devices. When a state of any of the chip enable signals is set to an enabled state, a state of the termination circuit enable signal generated by the signal generating circuit is set to an enabled state.

The present disclosure discloses a three-dimensional (3D) memory, which includes a peripheral wafer and an array wafer. The peripheral wafer includes a first peripheral structure and a second peripheral structure. The array wafer includes a substrate, a structure to be tested and multiple interconnecting portions. The substrate includes a first well region and a second well region. The array wafer includes the structure to be tested which has a first connecting portion, a second connecting portion, and multiple interconnecting portions. The first peripheral structure is connected to the first well region and the first connecting portion of the structure to be tested by the first interconnecting portion and the second interconnecting portion respectively. The second peripheral structure is connected to the second well region and the second connecting portion of the structure to be tested by the third interconnecting portion and the fourth interconnecting portion respectively.

A sense amplifier reference is generated with the same memory cell columns as data cells in order to match signal paths between the data and reference signals. Each row of data memory cells may have a corresponding set of reference cells, which greatly reduces the number of data cells supported by a reference, and in turn reduces the impact of process variations. A memory array may include data columns, a first reference column in the memory array configured to provide a logic 0 reference signal, and a second reference column in the memory array configured to provide a logic 1 reference signal. A circuit is configured to combine at least the logic 0 reference signal and the logic 1 reference signal to generate a reference signal for a sense amplifier to identify the data signal provided from the data columns.

A computer-implemented method includes fetching, by a controller, data using a plurality of memory channels of a memory system. The method further includes detecting, by the controller, that a first memory channel of the plurality of memory channels has not returned data. The method further includes marking, by the controller, the first memory channel from the plurality of memory channels as unavailable. The method further includes, in response to a fetch, reconstructing, by the controller, fetch data based on data received from all memory channels other than the first memory channel.

Embodiments of the present disclosure provide a memory detection method and detection apparatus, for detecting a current-leakage bitline. The method includes: a memory including a plurality of memory cells, a plurality of sense amplifiers, and the sense amplifier including a power line providing a low potential voltage and a power line providing a high potential voltage; writing first memory data to each of the memory cells; performing a reading operation after the first memory data is written; acquiring a first test result based on a difference between first real data and the first memory data; performing the reading operation again to read second real data in each of the memory cells; acquiring a second test result based on a difference between the second real data and second memory data; and acquiring a specific position of the current-leakage bitline based on the second test result and the first test result.