Memory devices are disclosed. A memory device may include a number of memory banks and a number of latch sets, wherein each latch set is associated with a memory bank. The device may also include a fuse array including a number of fuses. The device may further include circuitry configured to read data from a first set of fuses of the number of fuses and broadcast data from the first set of fuses to a first latch set of the number of latch sets. Further, in response to a repair result associated with the first set of fuses being a first state, the circuitry may be configured to read a second set of fuses and broadcast the second set of fuses to the first latch set. Methods of operating a memory device, and electronic systems are also disclosed.

A chip detection method includes: providing a chip to be tested, the chip having multiple one-time programmable memories (OTPMs); transmitting a test signal to the chip to maintain the OTPMs in the chip in a latched state; and detecting whether the chip emits a low-light signal, and if yes, determining that an OTPM is leaky. The chip detection method and device can detect an OTPM that is burnt through by mistake, and can also detect an OTPM that has slight leakage, thereby preventing a defective product with a potential burn-through risk from entering a subsequent production process.

A semiconductor apparatus including a semiconductor chip is disclosed. The semiconductor chip includes a modular region and a test circuit. The modular region includes a plurality of modular areas each including a memory cell array with redundant bit lines and a peripheral memory area storing at least redundant addresses. The test circuit retrieves the redundant addresses intrinsic to the semiconductor chip. The distribution of the redundant addresses are randomly formed related to a part or a whole of the modular area of the modular region. The test circuit outputs a random number generated from physical properties intrinsic to the semiconductor chip according to a specification code received from a physical-chip-identification measuring device.

An execution method of a firmware code, a memory storage device and a memory control circuit unit are disclosed. The method includes: executing a firmware code in a read only memory; after executing a first part of the firmware code, querying reference information in a reference memory according to index information in the firmware code; and determining, according to the reference information, to continuously execute a second part of the firmware code or switch to execute a replacement program code in the reference memory, so as to complete a startup procedure.

A dynamic random access memory (DRAM) comprises a plurality of primary data storage elements, a plurality of redundant data storage elements, and circuitry to receive a first register setting command and initiate a repair mode in the DRAM in response to the first register setting command. The circuitry is further to receive an activation command, repair a malfunctioning row address in the DRAM, receive a precharge command, receive a second register setting command, terminate the repair mode in the DRAM in response to the second register setting command, receive a memory access request for data stored at the malfunctioning row address, and redirect the memory access request to a corresponding row address in the plurality of redundant data storage elements.

A controller includes an internal memory to store an address and a memory control unit operatively coupled with the internal memory. The memory control unit includes logic to identify a malfunctioning address of primary data storage elements within an external memory device, the external memory device being another semiconductor device separate from the controller, store the malfunctioning address in the internal memory, and transmit, to the external memory device, a command to initiate a repair of the malfunctioning address using redundant data storage elements and an indication of an address associated with the malfunctioning address.

Methods, apparatuses and systems related to managing repair assets are described. An apparatus stores a repair segment locator and a repair address for each defect repair. The apparatus may be configured to selectively apply a repair asset to one of multiple sections according to the repair segment locator.

Apparatuses, systems, and methods for fuse based device identification. A device may include a number of fuses which are used to encode permanent information on the device. The device may receive an identification request, and may generate an identification number based on the states of at least a portion of the fuses. For example, the device may include a hash generator, which may generate the identification number by using the fuse information as a seed for a hash algorithm.

A latch circuit includes a plurality of latch sets, each including an enable latch and a plurality of address latches; and a plurality of latch-width adjusting circuits respectively corresponding to the latch sets, wherein, in each of the plurality of latch sets, the corresponding latch-width adjusting circuit is disposed between the enable latch of the corresponding latch set and the address latch adjacent to the enable latch, and couples the enable latch to the adjacent address latch depending on whether or not the corresponding latch set is used, at an end of a boot-up operation.

Methods, systems, and devices for completing memory repair operations interrupted by power loss are described. A command to perform a memory repair of a memory device may be received. A memory repair process of the memory device may be initiated, based on the command. The memory repair process may include programming fuse elements of the memory device. Information associated with the initiated memory repair process may be stored in a non-volatile memory. The memory repair process may be interrupted by a power interruption. During powerup of the memory device, it may be determined that the memory repair process was initiated and not completed before the powerup, based on the stored information. The memory repair process of the memory device may be continued, based on the determination. Upon completion of the memory repair process, the stored information may be cleared.