Some embodiments include apparatuses and methods having a memory structure included in a memory device and a control unit included in the memory device. The control unit can provide information obtained from the memory structure during a memory operation to a host device (e.g., a processor) in response to a command from the host device. If the control unit receives a notification from the host device indicating that the host device has detected an error in the information obtained from the memory structure, then a repair unit included in the memory device performs a memory repair operation to repair a portion in the memory structure.

Techniques for temperature control for multiple dies in an element. A temperature of a first die is measured, in an element comprising the first die and a second die. The second die includes at least a portion of a controller. The temperature of the first die is changed by adjusting activity, from the second die to the first die, based on a target temperature for the first die and the measured temperature for the first die.

A semiconductor device including an SRAM capable of sensing a defective memory cell that does not satisfy desired characteristics is provided. The semiconductor device includes a memory cell, a bit line pair being coupled to the memory cell and having a voltage changed towards a power-supply voltage and a ground voltage in accordance with data of the memory cell in a read mode, and a specifying circuit for specifying a bit line out of the bit line pair. In the semiconductor device, a wiring capacitance is coupled to the bit line specified by the specifying circuit and a voltage of the specified bit line is set to a voltage between a power voltage and a ground voltage in a test mode.

An IC includes an array of processor units, arranged in two or more subarrays. A subarray has a test generator, a multiplexer to apply a test vector to a datapath, and a test result output. It includes one or more processor units. A test result compressor is coupled with an output of the datapath, and compresses output data to obtain a test signature, which it stores in a signature register. The signature register is legible from outside the subarray. The datapath includes one or more memories and one or more ALUs. Test data travels through the full datapath, including the memories and the ALUs. ALU control registers are overridden during test to ensure a testable datapath.

The disclosure provides a method and apparatus of interleaved on-chip testing. The method merges a test setup for analog components with a test setup for digital components and then interleaves the execution of the digital components with the analog components. This provides concurrency via a unified mode of operation. The apparatus includes a system-on-chip test access port (SoC TAP) in communication with a memory test access port (MTAP). A built-in self-test (BIST) controller communicates with the MTAP, a physical layer, and a memory. A multiplexer is in communication with the memory and a phase locked loop (PLL) through an AND gate.

In one embodiment, a BIST (built-in self-test) engine performs BIST testing of embedded memory in an integrated circuit device (e.g., an FPGA) via an (e.g., hard-wired, dedicated, low-latency) bus from the configuration bitstream engine. During BIST testing, data is written into the embedded memory at-speed, which may require the bitstream engine to produce a higher frequency than originally used for configuration. Between consecutive write operations, the BIST engine is capable of reading the previously written set of data from the embedded memory and comparing that read-back data with the corresponding original set of data to determine whether a BIST error has occurred. By performing back-to-back write/read-back operations faster than the configuration speed and using a dedicated W/RB bus, BIST testing can be optimally performed without false-positive-invoking delays and undesirable resource utilization.

A memory includes an error detection circuit that identifies a faulty feature in an array of memory cells within the memory. A redundancy enable circuit functions to replace the faulty feature with a redundant feature. The error detection circuit and the redundancy enable circuit function concurrently with a read operation on the array of memory cells.

An aspect includes a method of streaming stress testing in a cache memory system. The method includes configuring, by a streaming stress generator, one or more streams of cache lines in the cache memory system to be accessed by a cache prefetch engine of a processor. One or more stream parameters are randomized to vary a streaming stress applied by the one or more streams to the cache memory system. The one or more streams are generated as read or write requests to the cache lines as prefetches from the cache prefetch engine absent a request for the cache lines from a processor core of the processor. A determination is made as to whether any faults are detected while the one or more streams are prefetched.

Embodiments relate to testing memory write operations. An aspect includes detecting a first write operation to a set of “n” divisions in a memory table, and defining a selected set of entries of an optimization checking table corresponding to the set of “n” divisions of the memory table. The aspect includes determining that at least one selected entry of the selected set of entries is not among an optimal set of entries of the checking table. The aspect further includes determining whether to generate an optimization error or to end an optimization analysis of the first write operation without generating the optimization error by comparing the first time stamps of one or both of the at least one selected entry and one or more optimal entries of the optimal set of entries to a temporal window defined by a predetermined duration.

A method includes specifying a target memory macro, and determining failure rates of function-blocks in the target memory macro based on an amount of transistors and area distributions in a collection of base cells. The method also includes determining a safety level of the target memory macro, based upon a failure-mode analysis of the target memory macro, from a memory compiler, based on the determined failure rate.