Apparatuses and methods for calibrating adjustable impedances of a semiconductor device are disclosed in the present application. An example apparatus includes a register configured to store impedance calibration information and further includes programmable termination resistances having a programmable impedance. The example apparatus further includes an impedance calibration circuit configured to perform a calibration operation to determine calibration parameters for setting the programmable impedance of the programmable termination resistances. The impedance calibration circuit is further configured to program the impedance calibration information in the register related to the calibration operation.

Embodiments of the present invention include a solid state storage device for reporting actual power consumption including an internal power metering unit, a memory including flash memory, one or more components comprising at least a controller and the memory, wherein the memory has stored thereon instructions that are configured to be executed by the controller, and one or more voltage rails connecting the power metering unit to the one or more components so that the power metering unit is capable of measuring power consumed by the one or more components of the storage device.

A system includes a memory device including a plurality of groups of memory cells and a processing device that is operatively coupled to the memory device. The processing device is to receive a request to determine a reliability of the plurality of groups of memory cells. The processing device is further to perform, in response to receipt of the request, a scan operation on a sample portion of the plurality of groups of memory cells to determine a reliability of the sample portion that is representative of the reliability of the plurality of groups of memory cells.

A system can predict memory device failure through identification of correctable error patterns based on the memory architecture. The failure prediction can thus account for the circuit-level of the memory rather than the mere number or frequency of correctable errors. A failure prediction engine correlates hardware configuration of the memory device with correctable errors (CEs) detected in data of the memory device to predict an uncorrectable error (UE) based on the correlation.

A memory system, and a method of operating the memory system, includes a memory device including a plurality of memory blocks. The memory system also includes a memory controller for controlling the memory device to perform a data copy operation of moving and storing valid data stored in a selected memory block among the plurality of memory blocks in a target block among the plurality of memory blocks. The memory controller is configured to control the memory device to perform the data copy operation by preferentially selecting a weak page among a plurality of pages included in the selected memory block rather than the other pages.

A method of operating a memory device comprises generating a target voltage using a pump circuit of the memory device, the target voltage to be applied to a word line or pillar of a memory cell of the memory device; providing an indication of current generated by the pump circuit after the pump circuit output reaches the target voltage; and determining when the current generated by the pump circuit is greater than a specified threshold current and generating a fault indication according to the determination.

Devices and techniques for performing copy-back operations in a memory device are disclosed herein. A trigger to perform a copy-back operation in relation to a section of data stored on the memory device can be detected. Circuitry of the memory device can then read the section of data at two voltage levels within a read window to obtain a first set of bits and a second set of bits respectively. The first and second sets of bits—which should be the same under normal circumstances—are compared to determine whether a difference between the sets of bits is beyond a threshold. If the difference is beyond a threshold, error correction is invoked prior to completion of the copy-back operation.

Methods, systems, and apparatuses for memory (e.g., DRAM) having an error check and scrub (ECS) procedure in conjunction with refresh operations are described. While a refresh operation reads the code words of a memory row, ECS procedures may be performed on some of the sensed code words. When the write portion of the refresh begins, a code word discovered to have errors may be corrected before it is written back to the memory row. The ECS procedure can be incremental across refresh operations, beginning, for example, each ECS at the code word where the pervious ECS for that row left off. The ECS procedure can include an out-of-order (OOO) procedure where ECS is performed more often for certain identified code words.

A method includes performing a first read operation involving a set of memory cells using a first voltage, determining a quantity of bits associated with the set of memory cells based on the first read operation, performing a second read operation involving the set of memory cells using a second voltage that is greater than the first voltage when the quantity of bits is above a threshold quantity of bits for the set of memory cells, and performing the second read operation involving the set of memory cells using a third voltage that is less than the first voltage when the quantity of bits is below the threshold quantity of bits for the set of memory cells.

The present disclosure generally relates to methods and systems for allocating free blocks as decommissioned blocks to replace bad blocks. In certain embodiments, when there are insufficient free blocks in a free block list to replace a bad or defective block for a CE, an FTL scans blocks stored in an unallocated block repository. If there are unallocated blocks available for the CE, one or more is reallocated as free blocks and used to replace the bad or defective block. When only one or no further unallocated blocks for the CE are available, the FTL places the CE in a read-only mode.