Respective life expectancies of a first data unit and a second data unit of the memory device is obtained. A first initial age value corresponding to the first data unit and a second initial age value corresponding to the second data unit are determined. A lower one of the first initial age value and the second initial age value is identified. A first media management operation on a corresponding one of the first data unit or the second data unit associated with the lower one of the first initial age value and the second initial age value is performed. A second media management operation on the first data unit and the second data unit is performed.

A non-volatile storage apparatus comprises one or more memory die assemblies, each of which includes an inference circuit positioned in the memory die assembly. The inference circuit is configured to use a pre-trained model (received pre-trained from a source external to the non-volatile storage apparatus and stored in a dedicated block in non-volatile memory) with one or more metrics describing current operation of the non-volatile storage apparatus in order to predict a defect in the non-volatile storage apparatus and perform a countermeasure to preserve host data prior to a non-recoverable failure in the non-volatile storage apparatus due to the defect.

An apparatus having a first circuit and a second circuit is disclosed. The first circuit may be configured to generate statistics of a region of a memory circuit as part of a read scrub of the region. The region may have multiple units of data. The memory circuit may be configured to store the data in a nonvolatile condition. The second circuit is generally configured to (i) track one or more parameters of the region based on the statistics, (ii) determine when one or more of the statistics of one or more outliers of the units in the region exceeds a corresponding threshold and (iii) track the parameters of the outlier units separately from the parameters of the region in response to exceeding the corresponding threshold. The parameters generally control one or more reference voltages used to read the data from the region.

Methods, systems, and devices for monitoring and adjusting access operations at a memory device are described to support integrating monitors or sensors for detecting memory device health issues, such as those resulting from device access or wear. The monitoring may include traffic monitoring of access operations performed at various components of the memory device, or may include sensors that may measure parameters of components of the memory device to detect wear. The traffic monitoring or the parameters measured by the sensors may be represented by a metric related to access operations for the memory device. The memory device may use the metric (e.g., along with a threshold) to determine whether to adjust a parameter associated with performing access operations received by the memory device, in order to implement a corrective action.

A memory system includes a semiconductor memory device and a memory controller configured to control the semiconductor memory device. The semiconductor memory device includes a memory cell array including a plurality of memory cells configured to store data, a refresh controller configured to control a refresh operation with respect to the plurality of memory cells, and an error monitoring circuit configured to generate error information by monitoring an error in the data stored in the memory cell array based on refresh sensing data provided from the memory cell array during the refresh operation. The memory controller includes an error correction code (ECC) circuit and is further configured to correct the error in the data stored in the memory cell array using the ECC circuit based on the error information.

A processing device coupled to the memory device can be configured to monitor respective raw bit error rates (RBERs) corresponding to a plurality of groups of memory cells of the memory device. The processing device can also be configured to responsive to determining that an RBER corresponding to a particular group of the plurality of groups of memory cells has met a criteria, adjust a read window budget corresponding to the particular group of memory cells.

Embodiments herein describe a memory system that includes a DRAM module with a plurality of individual DRAM chips. In one embodiment, the DRAM chips are per DRAM addressable (PDA) so that each DRAM chip can use a respective reference voltage (VREF) value to decode received data signals (e.g., DQ or CA signals). During runtime, the VREF value can drift away from its optimal value set when the memory system is initialized. To address possible drift in VREF value, the present embodiments perform VREF calibration dynamically. To do so, the memory system monitors a predefined criteria to determine when to perform VREF calibration. To calibrate VREF value, the memory system may write transmit data and then read out the test data to determine the width of a signal eye using different VREF values. The memory system selects the VREF value that results in the widest signal eye.

A method includes determining a quantity of refresh operations performed on a block of a memory device of a memory sub-system and determining a quantity of write operations and a quantity of read operations performed to the block. The method also includes determining the block is read dominant using the quantity of write operations and the quantity of read operations and determining whether the quantity of refresh operations has met a criteria. The method further includes, responsive to determining that the block is read dominant and that the quantity of refresh operations has met the criteria, modifying trim settings used to operate the block of the memory device.

The present invention provides a memory system in which a semiconductor memory device can be accessed properly. The memory system includes a memory controller and a semiconductor memory device. The memory controller sends a command, an address, and first checking data to the semiconductor memory device. When the semiconductor memory device receives first response information that indicates that no error has been detected, it sends or receives read data or write data from the semiconductor memory device. When the semiconductor memory device receives the command, the address, and the first checking data, it uses the first checking data to detect errors in the command and the address, and sends the first reply information when no error is detected, and when no error is detected in the command and the address, it sends or receives read data or write data from the semiconductor memory device.

Control logic in a memory device receives a request to perform a memory access operation on a memory array of the memory device and determines an operating temperature of the memory device. The control logic further modifies a default magnitude of a source voltage signal based on the operating temperature to a form a modified source voltage signal, causes the modified source voltage signal to be applied to the memory array, and performs the memory access operation on the memory array.