A memory system and a data processing system including the memory system may manage a plurality of memory devices. For example, the data processing system may categorize and analyze error information from the memory devices, acquire characteristic data from the memory devices and set operation modes of the memory devices based on the characteristic data, allocate the memory devices to a host workload, detect a defective memory device among the memory devices and efficiently recover the defective memory device.

An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to identify a set of embedded servo cells stored on the memory device; determine a read voltage offset by performing read level calibration based on the set of embedded servo cells; and apply the read voltage offset for reading a memory page associated with the set of embedded servo cells.

Methods, systems, and computer-readable media (transitory or non-transitory) are described herein for automatic backup and replacement of a storage device. According to an example, a storage failure for given storage device may be predicted. A backup process of the give storage device to a remote system may be initiated based on predicting the storage failure for the given storage device. The backup process may create a one-to-one image backup or a user data backup based on a predicted amount of time until the storage failure of the given storage device. A restore process of a new storage device at the remote system may be initiated upon completion of the backup process. The restore process may depend on the backup created during the backup process and/or various types of new storage devices that are available. The new storage device may be based on the given storage device.

A method of operating a memory device is provided. The method includes: receiving a first command from a controller; activating a page of a memory cell array based on the first command; reading data of the activated page; detecting an error from the read data; correcting the detected error to generate error correction data; writing back the error correction data to the activated page in based on the detected error being a single-bit error; and blocking write-back of the error correction data to the activated page based on the detected error being a multi-bit error.

Systems, apparatuses, and methods related to a flip-on-precharge disable operation are described herein. In an example, a flip-on-precharge disable operation can include activating a set of memory cells in a memory device to perform a memory access. The memory device can include a plurality of sets of memory cells corresponding to respective portions of an array of memory cells of the memory device. The flip-on-precharge disable operation can further include receiving signaling indicative of a command for a precharge operation on a set of the plurality of sets of memory cells. The signaling can include one or more bits that indicates whether to disable a randomly performed flip operation on the set of memory cells. The flip-on-precharge disable operation can include, in response to the one or more bits indicating to disable the flip operation, performing the precharge operation without randomly performing the flip operation on the set of memory cells.

According to one embodiment, a memory system includes a semiconductor memory device and a controller. The device includes a plurality of memory cells capable of storing at least first to third data and a word line coupled to the plurality of memory cells. The first data is determined by a first read operation including a first read level. The second data is determined by a second read operation including a second read level. The third data is determined by a third read operation including a third read level. The controller controls the semiconductor memory device to perform a forth read operation including the first and second read levels in a search operation for first to third read voltages corresponding to the first to third read levels, respectively.

An example method includes maintaining a first data structure comprising logical address to physical address mappings for managed units corresponding to a memory, and maintaining a second data structure whose entries correspond to respective physical managed unit addresses. Each entry of the second data structure comprises an activity counter field corresponding to the respective physical managed unit address and a number of additional fields indicating whether the respective physical managed unit address is in one or more of a number of additional data structures. The one or more additional data structures are accessed in association with performing at least one of a wear leveling operation on the respective physical managed unit address, and a neighbor disturb mitigation operation on physical managed unit addresses corresponding to neighbors of the respective physical managed unit address.

A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, a refresh control circuit, a scrubbing control circuit and a control logic circuit. The refresh control circuit generates refresh row addresses for refreshing a memory region on memory cell rows in response to a first command received from a memory controller. The scrubbing control circuit counts the refresh row addresses and generates a scrubbing address for performing a scrubbing operation on a first memory cell row of the memory cell rows whenever the scrubbing control circuit counts N refresh row addresses of the refresh row addresses. The ECC engine reads first data corresponding to a first codeword, from at least one sub-page in the first memory cell row, corrects at least one error bit in the first codeword and writes back the corrected first codeword in a corresponding memory location.

A semiconductor memory device includes a memory cell array, an error correction code (ECC) circuit, a fault address register and a control logic circuit. The memory cell array includes a plurality of memory cell rows. The scrubbing control circuit generates scrubbing addresses for performing a scrubbing operation on a first memory cell row based on refresh row addresses for refreshing the memory cell rows. The control logic circuit controls the ECC circuit such that the ECC circuit performs an error detection and correction operation on a plurality of sub-pages in the first memory cell row to count a number of error occurrences during a first interval and determines a sub operation in a second interval in the scrubbing operation based on the number of error occurrences in the first memory cell row.

A processing device, operatively coupled with the memory device, is configured to determine a first error rate associated a first set of pages of a plurality of pages of a data unit of a memory device, and a second error rate associated with a second set of pages of the plurality of pages of the data unit, determine a first pattern of error rate change for the data unit based on the first error rate and the second error rate, and responsive to determining that the first pattern of error rate change corresponds to a predetermined second pattern of error rate change, perform an action pertaining to defect remediation with respect to the data unit.