Methods, systems, and devices for storing and reading data at a memory device are described. A memory device may utilize one or more storage states to store data within a data word. The memory device may exhibit higher data leakage or more power consumption when storing or reading a first storage state compared to storing or reading one or more other storage states. In some cases, the memory device may generate a second data word corresponding to a first data word by modifying each symbol type of the first data word to generate a different symbol type for the second data word. A memory device may reduce the occurrence of a storage state associated with large data leakage, or high-power consumption, or both. Further, the memory device may generate and store an indicator indicating the transformation of a corresponding data word.

A caching system including a first sub-cache and a second sub-cache in parallel with the first sub-cache, wherein the second sub-cache includes: line type bits configured to store an indication that a corresponding cache line of the second sub-cache is configured to store write-miss data, and an eviction controller configured to evict a cache line of the second sub-cache storing write-miss data based on an indication that the cache line has been fully written.

In described examples, a memory module includes a memory array with a primary access port coupled to the memory array. Error correction logic is coupled to the memory array. A statistics register is coupled to the error correction logic. A secondary access port is coupled to the statistics register to allow access to the statistics register by an external device without using the primary interface.

A serial presence detect (SPD) device includes nonvolatile memory to store SPD information. Parity information suitable for single error correct and double error detect (SEC-DED) is also stored in association with the SPD information in the nonvolatile memory. The combination of SPD information and parity information is organized into codewords addressable at each memory location. During an initialization period occurring after a power on reset and before the SPD device is accepting I2C commands, the SPD device checks each memory location (codeword) for errors. Each error detected is counted to provide an indicator of device health. Before the initialization period expires, the SPD device writes a corrected codeword back to the nonvolatile memory.

Several embodiments of memory devices and systems having a variable logical memory capacity are disclosed herein. In one embodiment, a memory device can include a plurality of memory regions that collectively define a physical memory capacity and a controller operably coupled to the plurality of memory regions. The controller is configured to advertise a first logical memory capacity to a host device, determine that at least one of the memory regions is at or near end of life, and in response to the determination—send a notification to the host device that a logical memory capacity of the memory device will be reduced and then retire the at least one of the memory regions.

Described are memory modules that support different error detection and correction (EDC) schemes in both single- and multiple-module memory systems. The memory modules are width configurable and support the different EDC schemes for relatively wide and narrow module data widths. Data buffers on the modules support the half-width and full-width modes, and also support time-division-multiplexing to access additional memory components on each module in support of enhanced EDC.

A method can include, in an integrated circuit device: at a unidirectional command-address (CA) bus having no more than four parallel inputs, receiving a sequence of no less than three command value portions; latching each command value portion in synchronism with rising edges of a timing clock; determining an input command from the sequence of no less than three command value portions; executing the input command in the integrated circuit device; and on a bi-directional data bus having no more than six data input/outputs (IOs), outputting and inputting sequences of data values in synchronism with rising and falling edges of the timing clock. Corresponding devices and systems are also disclosed.

Systems and methods are disclosed, including rebuilding a logical-to-physical (L2P) data structure of a storage system subsequent to relocating assigned marginal group of memory cells of a memory array of the storage system, such as when resuming operation from a low-power state, including an asynchronous power loss (APL).

A memory device that performs internal ECC (error checking and correction) can treat an N-bit channel as two N/2-bit channels for application of ECC. The memory device includes a memory array to store data and prefetches data bits and error checking and correction (ECC) bits from the memory array for a memory access operation. The memory device includes internal ECC hardware to apply ECC, with a first group of a first half the data bits checked by a first half of the ECC bits in parallel with a second group of a second half of the data bits checked by a second half of the ECC bits.

A memory system and a data processing system including the memory system may manage a plurality of memory devices. For example, the data processing system may categorize and analyze error information from the memory devices, acquire characteristic data from the memory devices and set operation modes of the memory devices based on the characteristic data, allocate the memory devices to a host workload, detect a defective memory device among the memory devices and efficiently recover the defective memory device.