A system can validate multiple nonvolatile random-access memory (NVRAM) devices in parallel. The system can concurrently write a first data to a first volatile memory of a first NVRAM device and a second NVRAM device. The system can modify a first electrical power source that provides an electrical power output that is received by the first NVRAM device and is received by the second NVRAM device to modify a voltage of the electrical power from a first value to a second value to initiate the first NVRAM device and the second NVRAM device to respectively perform a vault. The system can reset the first electrical power source, causing the first NVRAM device and the second NVRAM device to reset. The system can verify whether the first NVRAM device and the second NVRAM device respectively store the first data in volatile memory subsequent to performing the resetting.

A signal detection system and a memory detection method are provided. The system includes a signal generator, generating a reference test signal based on an external parameter, the reference test signal being a clock signal satisfying a preset duty cycle, where a duty cycle test is performed on the reference test signal based on a test circuit, to determine whether a function of the test circuit is normal. If the function of the test circuit is normal, different portions under test are sequentially selected based on a test control signal, and the duty cycle test is performed, based on the test circuit, on a signal outputted by each of the selected portions under test. The portions under test include a signal converter and a write clock path.

According to one embodiment, a memory system includes: a controller configured to execute an error correction process on first data read from a first area at a first address of a memory device and determine a read level used for reading data at the first address according to a result of the correction process. The controller executes the correction process on first frame data of the first data. When the correction process on the first frame data has failed, the controller executes the correction process on second frame data of the first data. When the correction process on the second frame data has succeeded, the controller determines the read level based on a result of comparison between the second frame data and a result of the correction process on the second frame data.

The present application provides a memory test circuit and a device wafer including the memory test circuit. The memory test circuit is coupled to a memory array having intersecting first and second signal lines, and includes a fuse element and a transistor. The fuse element has a first terminal coupled to a first group of the first signal lines and a test voltage, and has a second terminal coupled to second and third groups of the first signal lines. The transistor has a source/drain terminal coupled to the second terminal of the fuse element and another source/drain terminal coupled to a reference voltage. The first group of the first signal lines are selectively coupled to the test voltage when the transistor is turned on, and all of the first signal lines are coupled to the test voltage when the transistor is kept off.

The present application provides a memory test circuit and a device wafer including the memory test circuit. The memory test circuit is coupled to a memory array having intersecting first and second signal lines, and includes a fuse element and a transistor. The fuse element has a first terminal coupled to a first group of the first signal lines and a test voltage, and has a second terminal coupled to second and third groups of the first signal lines. The transistor has a source/drain terminal coupled to the second terminal of the fuse element and another source/drain terminal coupled to a reference voltage. The first group of the first signal lines are selectively coupled to the test voltage when the transistor is turned on, and all of the first signal lines are coupled to the test voltage when the transistor is kept off.

Provided are an operating method of a host device, an operating method of a memory device, and a memory system. The operating method of a host device includes transmitting a request command for performing an eye-opening monitor (EOM) operation to a memory device, transmitting a parameter for performing the EOM operation to the memory device, transmitting pattern data for performing the EOM operation to the memory device, and receiving a first response signal including a result of the EOM operation performed based on the parameter and the pattern data from the memory device.

The present disclosure provides a method for detecting a memory and a device for detecting a memory. The memory includes first memory cells, second memory cells, bit lines, complementary bit lines, word lines, and a plurality of sense amplifiers, where each of the sense amplifiers is electrically coupled to a bit line and a complementary bit line; and the method includes: writing storage data into each of the first memory cells and each of the second memory cells; performing a read operation; obtaining a test result based on a difference between real data and the storage data; and obtaining a leakage position of the bit line and the word line or a leakage position the complementary bit line and the word line based on the test result.

The present disclosure provides a method for detecting a memory and a device for detecting a memory. The memory includes first memory cells, second memory cells, bit lines, complementary bit lines, word lines, and a plurality of sense amplifiers, where each of the sense amplifiers is electrically coupled to a bit line and a complementary bit line; and the method includes: writing storage data into each of the first memory cells and each of the second memory cells; performing a read operation; obtaining a test result based on a difference between real data and the storage data; and obtaining a leakage position of the bit line and the word line or a leakage position the complementary bit line and the word line based on the test result.

The present disclosure provides a test method and a test apparatus for a semiconductor device. The test method includes: forming a plurality of test values based on a first retention time range and a first step size, and sequentially testing a plurality of memory cells in the semiconductor device based on the plurality of test values in ascending order; determining, during tests corresponding to each test value, a memory cell whose retention time is less than the test value, and recording a position and corresponding test value of the memory cell whose retention time is less than the test value, to form first test data; a similar method is applied to form second test data; and determining, based on the first test data and the second test data, positions and corresponding test values of memory cells whose retention times fail to pass the tests.

The present disclosure provides a test method and a test apparatus for a semiconductor device. The test method includes: forming a plurality of test values based on a first retention time range and a first step size, and sequentially testing a plurality of memory cells in the semiconductor device based on the plurality of test values in ascending order; determining, during tests corresponding to each test value, a memory cell whose retention time is less than the test value, and recording a position and corresponding test value of the memory cell whose retention time is less than the test value, to form first test data; a similar method is applied to form second test data; and determining, based on the first test data and the second test data, positions and corresponding test values of memory cells whose retention times fail to pass the tests.