A multicycle path circuit capable of operating at a functional mode and an at-speed test mode. The multicycle path circuit includes an on-chip controller configured to receive an on-chip clock signal and modulate the on-chip clock signal to provide a first clock signal to a first circuit and a second clock signal to a second circuit. The first clock signal and the second clock signal are in a multicycle phase relationship. The on-chip controller is configured to ensure the clock paths to and from the second circuit to be the same for the functional mode and the at-speed test mode and therefore to avoid hold and setup timing conflict between these modes,

A memory includes: an input circuit, configured to: receive an outside clock signal, and output a first test clock signal; a test path selection circuit, connected to the input circuit, and configured to output a second test clock signal according to a read clock command; and an output circuit, connected to the test path selection circuit, and configured to convert the second test clock signal into a third test clock signal and output the third test clock signal to outside of the memory. In the embodiments of the disclosure, a time delay of inputting a clock signal into each chip under test is quantified, to acquire an actual output delay of the chip, thereby improving the accuracy of parallel tests of a plurality of chips.

Various embodiments include a memory device that is capable of performing command address interface training operations, to determine that certain timing conditions are met, with fewer I/O pins relative to prior approaches. Prior approaches for command address interface training involve loading data via a set of input pins, a clock signal, and a clock enable signal that identifies when the input pins should be sampled. Instead, the disclosed memory device generates a data pattern within the memory device that matches the data pattern continuously being transmitted to the memory device by an external memory controller. The memory device compares the generated data pattern with the received data pattern and transmits the result of the comparison on one or more data output pins. The memory controller receives and analyzes the result of the comparison to determine whether the command address interface training passed or failed.

Embodiments of the disclosure are drawn to apparatuses and methods for a multi-bit duty cycle monitor. A clock signal may be provided to a memory in order to synchronize one or more operations of the memory. The clock signal may have a duty cycle which is adjusted by a duty cycle adjustor of the memory. The duty cycle of the adjusted clock signal may be monitored by a multi-bit duty cycle monitor. The multi-bit duty cycle monitor may provide a multi-bit signal which indicates if the duty cycle of the adjusted clock signal is above or below a target duty cycle value (or if the duty cycle is outside tolerances around the target duty cycle). The multi-bit duty cycle monitor may provide the multi-bit signal while access operations of the memory are occurring.

A testing tool includes a clock generation circuit generating a test clock and outputting the test clock via a test clock output pad, data processing circuitry clocked by the test clock, and data output circuitry receiving data output from the data processing circuitry and outputting the data via an input/output (IO) pad, the data output circuitry being clocked by the test clock. The testing tool also includes a programmable delay circuit generating a delayed version of the test clock, and data input circuitry receiving data input via the IO pad, the data input circuitry clocked by the delayed version of the test clock. The delayed version of the test clock is delayed to compensate for delay between transmission of a pulse of the test clock via the test clock output pad to an external computer and receipt of the data input from the external computer via the IO pad.

Provided is a test apparatus for testing a device under test (DUT), the apparatus operating at an operating frequency that is lower than an operating frequency of the DUT. The test apparatus includes a clock source which generates a clock according to the operating frequency of the test apparatus, a clock multiplier configured to multiply the generated clock source by a multiplication number which is set according to the operating frequency of the DUT and output a first clock for the DUT, a phase converter configured to shift a phase of the generated clock according to the multiplication number and output a plurality of second clocks having different phases, and a test pattern comparator configured to sequentially collect pieces of data from the DUT by sequentially applying the plurality of second clocks having different phases.

A clock generation circuit, a memory and a clock duty cycle calibration method are provided; the clock generation circuit comprises: an oscillation circuit, configured to generate a first oscillation signal and a second oscillation signal, a frequency of the first oscillation signal is same as a frequency of the second oscillation signal, and a phase of the first oscillation signal is opposite to a frequency of the second oscillation signal; a comparison unit, configured to receive the first oscillation signal and the second oscillation signal, and compare the duty cycle of the first oscillation signal and/or the duty cycle of the second oscillation signal; and a logical unit, connected to the comparison unit and the oscillation circuit, and configured to control the oscillation circuit according to an output result of the comparison unit, so that the duty cycle reaches a preset range.

A memory includes: a clock generation circuit, configured to generate a first oscillation signal and a second oscillation signal. The first oscillation signal and the second oscillation signal have a same frequency but opposite phases, and a duty cycle of the first oscillation signal and a duty cycle of the second oscillation signal are both within a first preset range. The memory further includes a differential input circuit, which is configured to receive a first external signal and a second external signal, and generate a first internal signal and a second internal signal. The clock generation circuit is configured to monitor the duty cycle of the first internal signal or the duty cycle of the second internal signal, and enable the duty cycle of the first internal signal or the duty cycle of the second internal signal to be within a second preset range.

A method for testing a memory chip includes: in response to read command for the memory chip, controlling clock signal to be kept in first state within first preset time period and at the same time controlling complementary clock signal to be kept in second state within first preset time period; in response to clock signal kept in the first state and complementary clock signal kept in the second state, keeping data strobe signal in the first state within second preset time period and at the same time keeping complementary data strobe signal in the second state within the second preset time period; and when the data strobe signal and the complementary data strobe signal are kept in first and second states respectively, controlling first and second driving modules connected respectively to data strobe terminal and complementary data strobe terminal to operate and measure first and second resistance values respectively.

A circuit includes a dynamic core data register (DCDR) cell that includes a data register, a shift register and an output circuit to route the output state of the data register or the shift register to an output of the DCDR in response to an output control input. A clock gate having a gate control input controls clocking of the shift register in response to a first scan enable signal. An output control gate controls the output control input of the output circuit and controls which outputs from the data register or the shift register are transferred to the output of the output circuit in response to a second scan enable signal. The first scan enable signal and the second scan enable signal to enable a state transition of the shift register at the output of the DCDR.